NXP Semiconductors MWCT101 S Series, Reference Manual

Page: 239 / 1761

The register maps of the peripherals are located on 4-KB boundaries. Each peripheral is
allocated one or more 4-KB block(s) of the memory map.
14.3 Memory map/register definition
The 32-bit peripheral bridge registers can be accessed only in supervisor mode by trusted
bus masters. Additionally, these registers must be read from or written to only by a 32-bit
aligned access. The peripheral bridge registers are mapped into the Peripheral Access
Control Register A PACRA[PACR0] address space.
14.3.1 AIPS register descriptions
14.3.1.1 AIPS Memory map
AIPS_Lite base address: 4000_0000h
Offset Register Width
(In bits)
Access Reset value
0h Master Privilege Register A (MPRA) 32 RW 2C36_0000h
20h Peripheral Access Control Register (PACRA) 32 RW 5400_0000h
24h Peripheral Access Control Register (PACRB) 32 RW 4400_0400h
2Ch Peripheral Access Control Register (PACRD) 32 RW 4400_0000h
40h Off-Platform Peripheral Access Control Register (OPACRA) 32 RW 4400_4444h
44h Off-Platform Peripheral Access Control Register (OPACRB) 32 RW 0004_4440h
48h Off-Platform Peripheral Access Control Register (OPACRC) 32 RW 0440_0044h
4Ch Off-Platform Peripheral Access Control Register (OPACRD) 32 RW 4444_0400h
50h Off-Platform Peripheral Access Control Register (OPACRE) 32 RW 4000_0040h
54h Off-Platform Peripheral Access Control Register (OPACRF) 32 RW 4444_4400h
58h Off-Platform Peripheral Access Control Register (OPACRG) 32 RW 0040_4400h
5Ch Off-Platform Peripheral Access Control Register (OPACRH) 32 RW 0040_0000h
60h Off-Platform Peripheral Access Control Register (OPACRI) 32 RW 0404_4444h
64h Off-Platform Peripheral Access Control Register (OPACRJ) 32 RW 0044_4044h
68h Off-Platform Peripheral Access Control Register (OPACRK) 32 RW 4404_0040h
6Ch Off-Platform Peripheral Access Control Register (OPACRL) 32 RW 0400_0444h
Chapter 14 Peripheral Bridge (AIPS-Lite)
MWCT101xS Series Reference Manual, Rev. 3, 07/2019
NXP Semiconductors 239