NXP Semiconductors MWCT101 S Series, Reference Manual

Page: 1432 / 1761

46.3.1.13.1 Offset
Register Offset
MCCR0 48h
46.3.1.13.2 Function
The MCCR0 cannot be changed when the I2C master is enabled and is used for standard,
fast, fast-mode plus and ultra-fast transfers.
46.3.1.13.3 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R 0
DATAVD
0
SETHOLD
W
Reset
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R 0
CLKHI
0
CLKLO
W
Reset
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
46.3.1.13.4 Fields
Field Function
31-30
—
Reserved
29-24
DATAVD
Data Valid Delay
Minimum number of cycles (minus one) that is used as the data hold time for SDA. Must be configured
less than the minimum SCL low period.
23-22
—
Reserved
21-16
SETHOLD
Setup Hold Delay
Minimum number of cycles (minus one) that is used by the master
• as the hold time for a START condition
• as the setup and hold time for a repeated START condition
• as the setup time for a STOP condition
The setup time is extended by the time it takes to detect a rising edge on the external SCL pin. Ignoring
any additional board delay due to external loading, this time is equal to (2 + FILTSCL) / 2^PRESCALE
cycles.
15-14 Reserved
Table continues on the next page...
Memory Map and Registers
MWCT101xS Series Reference Manual, Rev. 3, 07/2019
1432 NXP Semiconductors