NXP Semiconductors MWCT101 S Series, Reference Manual

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FTM input clock
CNT
channel (n) input
CHF bit
C(n)V XX
0x27
selected channel (n) input event: rising edge
NOTE
Channel (n) input after its synchronizer and filter
MOD = 0xFFFF
CNTIN = 0x0000
PS[2:0] = 3'b000
ICRST = 1'b1
... 0x27 ... 0x00 0x01 0x02 0x03 0x26 0x25 0x24 0x23 0x22 0x21 0x20
Figure 41-20. Example of the Input Capture mode with ICRST = 1
NOTE
• It is expected that the ICRST bit be set only when the
channel is in input capture mode.
• If the FTM counter is reset because the channel is in input
capture mode with ICRST = 1, then the prescaler counter
(
Prescaler ) is also reset.
41.5.6 Output Compare mode
The Output Compare mode is selected when:
• DECAPEN = 0
• MCOMBINE = 0
• COMBINE = 0
• CPWMS = 0, and
• MSB:MSA = 0:1
In Output Compare mode, the FTM can generate timed pulses with programmable
position, polarity, duration, and frequency. When the counter matches the value in the
CnV register of an output compare channel, the channel (n) output can be set, cleared, or
toggled.
When a channel is initially configured to Toggle mode, the previous value of the channel
output is held until the first output compare event occurs.
The CHF bit is set and the channel (n) interrupt is generated if CHIE = 1 at the channel
(n) match (FTM counter = CnV).
Chapter 41 FlexTimer Module (FTM)
MWCT101xS Series Reference Manual, Rev. 3, 07/2019
NXP Semiconductors 1203