NXP Semiconductors MWCT101 S Series, Reference Manual

Page: 1189 / 1761

Field Function
VAL See the field VAL of the register CnV.
15-11
FRACVAL
Channel (n) Match Fractional Value
The channel (n) match fractional value is used in the PWM edge dithering. This value is added to the
channel (n) internal accumulator at the end of each PWM period.
Writes to the field FRACVAL are done on its write buffer. The FRACVAL is updated with its write buffer
value according to
Registers updated from write buffers . If FTMEN = 0, a write to CnSC register resets
manually this write coherency mechanism.
10-0
—
Reserved
41.5 Functional Description
41.5.1 Clock source
The FTM has only one clock domain: the FTM input clock.
41.5.1.1 Counter clock source
The CLKS[1:0] bits select one of three possible clock sources for the FTM counter or
disable the FTM counter. After any chip reset, CLKS[1:0] = 0:0 so no clock source is
selected.
The CLKS[1:0] bits may be read or written at any time. Disabling the FTM counter by
writing 0:0 to the CLKS[1:0] bits does not affect the FTM counter value or other
registers.
The fixed frequency clock is an alternative clock source for the FTM counter that allows
the selection of a clock other than the FTM input clock or an external clock. This clock
input is defined by chip integration. Refer to the chip specific documentation for further
information. Due to FTM hardware implementation limitations, the frequency of the
fixed frequency clock must not exceed 1/2 of the FTM input clock frequency.
The external clock passes through a synchronizer clocked by the FTM input clock to
assure that counter transitions are properly aligned to FTM input clock
transitions.Therefore, to meet Nyquist criteria considering also jitter, the frequency of the
external clock source must not exceed 1/4 of the FTM input clock frequency.
Chapter 41 FlexTimer Module (FTM)
MWCT101xS Series Reference Manual, Rev. 3, 07/2019
NXP Semiconductors 1189