NXP Semiconductors MPC5644A, Reference Manual, Page: 986 / 1735

Enhanced Time Processing Unit (eTPU2)
MPC5644A Microcontroller Reference Manual, Rev. 6
986 Freescale Semiconductor
With this system configuration, worst-case service time for each active channel is determined as follows:
a) Longest thread of PWM is 24 CPU clocks with four RAM accesses.
24 + ((4 RAM a1) * 0 * 2 CPU clock waits) = 24 CPU clocks
Channels 0-2 worst-case service time = 24 CPU clocks.
b) Longest thread of PPWA in mode 0 is 44 CPU clocks with nine RAM accesses.
44 + ((9 RAM ac1)* 0 * 2 CPU clock waits) = 44 CPU clocks
Channel 8 worst-case service time = 44 CPU clocks.
c) Longest thread of DIO is ten CPU clocks with four RAM accesses.
10 + ((4 RAM a1) * 0 * 2 CPU clock waits) = 10 CPU clocks
Channel 15 worst-case service time = 10 CPU clocks.
To find the WCL for channel 0, assume channel 0 has just finished service.
Map the channels in the H-M-H-L-H-M-H sequence. See Figure 24-72 .
Figure 24-72. Worst-case latency for channel 0 (first try)
Conclusion: with this system configuration, worst-case latencies for channels 0 and 1 are too
high (WCL for channel 1 is the same as WCL for channel 0). Try a different system
configuration.
Second-Try system configuration
The second-try system configuration is shown in Table 24-126 .
8 Middle PPWA at 5 kHz (needs an 80-µs WCL)
15 Low DIO as input at rate of 1 ms
1
0% RAM collision rate
2
CPU clock rate = 40 MHz, or 60 ns per clock period
Table 24-125. First-Try system configuration
Channel Priority Function
1
,
2
TPU CH0 WCL TIM 1 TPU CH0 WCL TIM 1
= 10-CYCLE TIME SLOT TRANSITION
= 4-CYCLE NOP INSTRUCTION
CHANNEL 0
SERVICED
WORST CASE LATENCY
H M H L H M H H
CHANNEL 8
SERVICED
CHANNEL 1
SERVICED
CHANNEL 15
SERVICED
CHANNEL 2
SERVICED
M H L
CHANNEL 0
SERVICED