NXP Semiconductors MPC5644A, Reference Manual, Page: 981 / 1735

Enhanced Time Processing Unit (eTPU2)
MPC5644A Microcontroller Reference Manual, Rev. 6
Freescale Semiconductor 981
Finding the WCL for PWM on Channel 0
The following shows how to find the WCL for PWM on channel 0.
1. Find the worst-case service time for each active channel.
a) Longest thread of PWM is 24 CPU clocks with four RAM accesses.
24 + ((4 RAM a1) * 0.09 * 2 CPU clock waits) = 24.9 CPU clocks, rounded up to 25
CPU clocks (since there are no partial clock periods)
Channel 0 worst-case service time = 25 CPU clocks.
b) Longest thread of PPWA in mode 0 is 44 CPU clocks with nine RAM accesses.
44 + ((9 RAM a1) * 0.09 * 2 CPU clock waits) = 45.8 CPU clocks, rounded up to 46
CPU clocks
Channel 1 worst-case service time = 46 CPU clocks.
c) Longest thread of DIO is ten CPU clocks with four RAM accesses.
10 + ((4 RAM a1) * 0.09 * 2 CPU clock waits) = 10.9 CPU clocks, rounded up to 11
CPU clocks
Channel 2 worst-case service time = 11 CPU clocks.
2. Assume channel 0 has just been serviced and that channels 1 and 2 are continuously requesting
service. Using the H-M-H-L-H-M-H time-slot sequence, map the channels that are granted for
each time slot. See
Figure 24-69 .
Figure 24-69. Next Servicing for Channel 0
Channel 1 will be serviced in the middle-priority time slot before channel 0 is serviced again.
3. Add time for the six-clock CPU time-slot transitions. See Figure 24-69 and Table 24-122 .
Table 24-121. System configuration example
Channel Priority Function
1
,
2
1
9% RAM Collision Rate (RCR)
2
CPU clock rate = 40 MHz, or 25 ns per clock period
0 High PWM (driving a DC motor)
1 Middle PPWA (Mode 0, measuring the DC motor speed)
2 Low DIO (Input)
TPU CH0 WCL TIM TPU CH0 WCL TIM
CHANNEL 0
SERVICED
WORST CASE LATENCY
CHANNEL 0
H M H L H M H H
CHANNEL 1
SERVICED
CHANNEL 0
SERVICED
= 10-CYCLE TIME SLOT TRANSITION
= 4-CYCLE NOP INSTRUCTION