NXP Semiconductors MPC5644A, Reference Manual, Page: 979 / 1735

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Figure 24-68. First-pass worst-case latency
To estimate worst-case latency:
• Find the worst-case service time for each active channel.
• Using the H-M-H-L-H-M-H time-slot sequence, map the channels that are granted for each time slot.
• Add time for six-clock time-slot transitions.
Finding the worst-case service time for each active channel
A table for eTPU functions should list the longest threads (not counting initialization threads) for the functions, and the number of
eTPU SPRAM accesses in the longest thread (semaphored and non semaphored). These figures will be used for estimating
Microengine wait time.
Table 24-120 is an example for old TPU functions in which there are only simple parameter RAM accesses.
It does not take into consideration the CDC operation and Microengine to Microengine communication.
The worst-case service time for each channel is: (CPCR = CCR = 0)
Longest ((number of RAM accesses in longest 1) * RCR * 2 clocks).
Note that the formula adds 1 RAM accesses for the parameter preload that occurs during TST. There are actually three accesses during
TST, but only the first one can receive wait-states.
Table 24-120. Longest threads and RAM accesses for old TPU functions
Function Longest thread RAM accesses
DIO 10 4
ITC 40 (no linking)
42 (linking)
7
OC 40 7
Channel X
Serviced
Worst-Case Latency Channel X
Other Channels Serviced
Channel X
Serviced Next