NXP Semiconductors MPC5644A, Reference Manual, Page: 963 / 1735

Enhanced Time Processing Unit (eTPU2)
MPC5644A Microcontroller Reference Manual, Rev. 6
Freescale Semiconductor 963
either in halt (device debug request asserted) or idle state (device debug request negated), but halt
enables several other features (see below).
• Occurrence of any of the hardware breakpoint conditions. See Section 24.5.10.2.3, Hardware
breakpoints , for details.
• Execution of a single-step microinstruction: microengine returns to halt state after executing a
single microinstruction while in halt state. See
Section 24.5.10.2.6, Single-step execution , and
Section 24.5.10.2.7, Forced microinstruction execution , for details.
When microengine enters halt state, it automatically triggers the following actions:
• Suspends input signal sampling and filters (respective engine channels only), if signal
ndedi_stop_pins is asserted at the Debug Interface.
• Releases the SPRAM arbitration for Host or CDC accesses, no matter if microengine was halted
in the middle of a dual-parameter (back-to-back) access.
• Stops TCR1/2 clocks of the respective engine, if signal ndedi_stop_tcr is asserted at the Debug
Interface.
• If the other engine is also in halt state or stopped, allows turning ETPU_MCR VIS bit to 1.
If all halt conditions are cleared when VIS = 1, microengine(s) keep on halt state until VIS = 0, when it
automatically exits halt state, except on single-step (see
Section 24.5.10.2.6, Single-step execution ), so
that single-step execution is ignored while VIS = 1.
MDU continues executing until it finishes any ongoing operation even if microengine is in halt state,
except when the halted instruction is an END.
There are two kinds of halt state, depending on the previous microengine state when halted:
1. halt_idle , if the engine was not executing a thread when halted; the engine cannot leave halt_idle
to fetch instructions, so one cannot single-step or follow a program flow; it can, however, execute
forced instructions (see
Section 24.5.10.2.7, Forced microinstruction execution ).
2. halt_exec , if the engine was executing a thread when halted. The engine can single-step and
continue a program flow from halt_exec.
When microengine exits halt state, any dependable action is suspended and, if exiting halt_exec, the
instruction pointed by the PC is fetched, while the instruction already fetched before halt is executed. Note
that both the PC and the prefetched instructions can be modified during halt state, with a forced execution
of a branch instruction (see
Section 24.5.10.2.7, Forced microinstruction execution ).
24.5.10.2.3 Hardware breakpoints
Microengine can enter halt state through a command from the Debug Interface, configuring a hardware
breakpoint. Hardware breakpoints can halt the microengine on specific conditions, listed below. These
conditions depend on NDEDI configuration.
• CHAN register assignment (only by microcode, not by time slot transition).
• SPRAM read and/or write to a given address and/or write data. The breakpoint is always qualified
by the SPRAM address, but the following variations are allowed:
— break on write only, read only, or read-and-write.