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Enhanced Time Processing Unit (eTPU2)
MPC5644A Microcontroller Reference Manual, Rev. 6
Freescale Semiconductor
857
If a channel service needs to postpone a programmed match, MEF assures that microcode wins the race
against match event after time slot transition (only for IPAC = 0xx).
Note that a match event may be lost during the periods when MEF is negated only if:
•
the match comparator is configured for “equal-only” behavior, and
•
IPACA/B = 0xx, and
•
TCR increments at the rate of system clock divided by 2 or faster.
When the comparator is configured as “greater-equal”, the match event that occurred when MEF was
negated may be recognized after MEF is asserted again, due to the “greater than” condition.
24.5.5.2.3
MRLEA/B – Match Recognition Latch Enable
MRLEA/B is negated upon the assertion of its respective MRLA/B. In blocking match channel modes it
may also be negated together with the assertion of the twin MRLB/A. The MRLEA/B bits ensure that data
captured due to the first match event will not be overwritten when MRLA/B is negated: due to
greater-equal comparison, the match condition continues to be true, but should not cause another capture
event.
In addition to negation by local match event, the microcode can negate both MRLEA and MRLEB, to
block pending matches, and also MRLA/B, individually. This action will prevent future match events from
the selected channel.
Writing the MatchA/B registers by microcode to schedule the next match values sets MRLEA and/or
MRLEB and enables new matches. This setting overrides the MRLE negation conditions due to channel
logic or microcode (see
Section 24.5.5.4, Channel Modes
). By combining write to Match A/B with
MRLEA/B negation microinstructions, the microcode can negate one MRLE while asserting the other.
NOTE
If the MRLE negation conditions continue after writing MatchA/B registers,
the respective MRLE does not keep asserted. For instance, if MRL = 1 and
a match is programmed for a time value in the past during a thread with
MEF = 1, then MRLE will be cleared soon after MatchA/B is written, even
though a match does not occur (because MRL was already asserted, neither
captures nor pin toggles occur).
When the match register is updated (with MRLE already asserted before) and field MRLA/B = 1 (no clear,
see
Section 24.5.9.3.6, Clear transition/match event registers
) and MRLA/B flag is zero, the eTPU behaves
exactly as the TPU, that is: a match that comes concurrently with the rewrite of the match register,
matching the old value, sets the MRL, as if the setting of the MRLE due to match register write had
precedence over its clear by the match at that moment. After this simultaneous operation, the MRLE value
stays at 1, and the captured time base value, if any, reflects the match value.
When the match register is updated (with MRLE already asserted before) and field MRLA/B = 0 (clear
MRL, see
Section 24.5.9.3.6, Clear transition/match event registers
) and MRLA/B flag is zero, the match
captures will occur, the MRLA/B flag will keep negated, and MRLE will stay asserted. If a match is
reprogrammed on TCR1 running at T2/T4 timing (TCR1CS = 1, see
eTPU Time Base Configuration Register
), a match can occur after MRLA/B is cleared, together with the
Summary of Contents for MPC5644A
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