NXP Semiconductors MPC5644A, Reference Manual, Page: 774 / 1735

Enhanced Time Processing Unit (eTPU2)
MPC5644A Microcontroller Reference Manual, Rev. 6
774 Freescale Semiconductor
Figure 24-5. ETPU_MISCCMPR Register
24.4.2.4 ETPU_SCMOFFDATAR – eTPU SCM Off-range Data Register
When read accesses are made, either by the host or an eTPU2 microengine, to addresses above the limit
corresponding to the SCMSIZE value in the ETPU_MCR, the value read comes from the
ETPU_SCMOFFDATAR.
The host can program the register at initialization with an opcode value with operations that try to protect
or recover the system from runaway code, for instance: terminate the thread, clear channel flags, disable
match and transition service requests, issue an interrupt, or jump to an error recovery procedure. Writes to
unimplemented addresses do not return an error and can write on unspecified mirror addresses, so they
should be avoided.
The reset value is MCU dependent.
Offset: eTP 0x00C Access: User read/write
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
R ETPUMISCCMP[31:16]
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R ETPUMISCCMP[15:0]
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
= Unimplemented or Reserved
Table 24-7. ETPU_MISCCMPR field description
Field Description
0-31 ETPUMISCCMP[31:0]—Expected Multiple Input Signature Register value
See Section 24.5.10.3.1, SCM Test – Multiple input signature calculator .