NXP Semiconductors MPC5644A, Reference Manual, Page: 662 / 1735

Configurable Enhanced Modular IO Subsystem (eMIOS200)
MPC5644A Microcontroller Reference Manual, Rev. 6
662 Freescale Semiconductor
Figure 22-13 shows both the Unified Channel Control and Datapath block diagram. The control block is
responsible for the generation of signals to control the multiplexes in the Datapath sub-block. Each mode
is implemented by a dedicated logic independent from others modes, thus allowing to optimize the logic
by disabling the mode and therefore its associated logic. The unused gates are removed during the
synthesis phase. Targeting the logic optimization, a set of registers is shared by the modes thus providing
sequential events to be stored.
The Datapath block provides the channel A and B registers, the internal time base and comparators.
Multiplexors select the input of comparators and data for the registers inputs, thus configuring the datapath
in order to implement the channel modes. The outputs of A and B comparators are connected to the control
block.
Figure 22-13. Unified Channel Control and Datapath block diagrams
A2
B2
B1
A1 CNT
local counter bus
global counter bus
A Comparator
BSL[0]
BSL[1]+logic
BSL[1]+logic
BSL[1]+logic
internal counter
[B/C/D]
B Comparator
Datapath
Control Block
co
ntr
o
l si
gnals
input
filter
input
mode 0
logic
General
Purpose
Registers
mode 1
logic
mode n
logic
MODE
decoder
MODE
register
==
==
[A]