NXP Semiconductors MPC5644A, Reference Manual, Page: 561 / 1735

Frequency-modulated phase locked loop (FMPLL)
MPC5644A Microcontroller Reference Manual, Rev. 6
Freescale Semiconductor 561
• Lock detect circuitry reports when the FMPLL has achieved frequency lock and continuously
monitors lock status to report loss of lock conditions
— User-selectable ability to generate an interrupt request upon loss of lock
— User-selectable ability to generate a system reset upon loss of lock
• Clock quality monitor (CQM) module provides loss-of-clock detection for the FMPLL reference
and output clocks
— User-selectable ability to generate an interrupt request upon loss of clock
— User-selectable ability to generate a system reset upon loss of clock
— Backup clock (reference clock or FMPLL free-running) can be applied to the system in case of
loss of clock
17.2.3 Modes of operation
Upon reset, the operational mode is bypass with PLL running, and the source of the reference clock, either
the crystal oscillator or external clock, is determined by the reset value of the CLKCFG[2] bit of the
FMPLL_ESYNCR1. The reset state of this bit comes from an external signal to the module connected to
a package pin called PLLREF. After reset, a different operational mode can be selected by writing to
FMPLL_ESYNCR1[CLKCFG]. The available modes are specified in
Table 17-2 .
At reset the FMPLL is enabled, but the reset value of the predivider may be set by the SoC integration to
inhibit the clock to the PLL, making the VCO run within its free-running frequency range of 25 MHz to
125 MHz, unconnected from the system clock (since bypass is the default mode at reset). If using crystal
reference, after power-on reset the Clock Quality Monitor (CQM) will inhibit the system clock and keep
system reset asserted while the crystal oscillator has not stabilized. The PLLREF input must be kept stable
during the whole period while system reset is asserted.
Table 17-2. Clock mode selection
CLKCFG[0] CLKCFG[1]
1
1
CLKCFG[1] is not writable to zero while CLKCFG[0] = 1.
CLKCFG[2]
2
2
The reset state of this bit is determined by the logical state applied to the PLLREF pin.
Clock mode
0 0 0 Bypass mode with external reference and PLL off
0 0 1 Bypass mode with crystal reference and PLL off
0 1 0 Bypass mode with external reference and PLL running
0 1 1 Bypass mode with crystal reference and PLL running
1 0 0 Reserved
1 0 1 Reserved
1 1 0 Normal mode with external reference
1 1 1 Normal mode with crystal reference