NXP Semiconductors MPC5644A, Reference Manual, Page: 435 / 1735

System Integration Unit (SIU)
MPC5644A Microcontroller Reference Manual, Rev. 6
Freescale Semiconductor 435
16.6.15.48 Pad Configuration Registers 75–82 (SIU_PCR75–SIU_PCR82)
The SIU_PCR75–SIU_PCR82 registers control the pin function, direction, and static electrical attributes
of the MDO[4:11]_GPIO[75:82] pins. GPIO is the default function at reset for these pins.
NOTE
The full port mode (FPM) and NEXCFG bits in the Nexus port controller
(NPC) port configuration register control whether these pins function as
MDO[4:11] or GPIO[75:82]. When the FPM and NEXCFG bits are set, the
NPC enables the MDO port enable, and disables GPIO. When the FPM or
NEXCFG bit is cleared, the NPC disables the MDO port enable, and enables
GPIO.
16.6.15.48.1 Pad Configuration Register 75 (SIU_PCR75)
Figure 16-63. Pad Configuration Register (SIU_PCR75)
Table 16-65. SIU_PCR70 PA values
Signal Name Module Description I/O
1,2
1
In cases where an I/O function can be either an input or an output, I/O direction is specified using
the IBE and OBE bits. Set IBE = 1 for input or OBE = 1 for output.
2
For I/O functions that change direction dynamically, such as the external data bus, switching
between input and output is handled internally and the IBE and OBE bits are ignored.
PA value
Primary TA EBI Transfer
acknowledge I/O 0b001
ALT1 TS EBI Transfer start O 0b010
GPIO GPIO[70] SIU GPIO I/O 0b000
S0xD6
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
R
0 0 0 0 PA OBE
1
1
This bit applies only to GPIO operation.
IBE
1
0 0 ODE
2
2
The ODE bit should be set to zero for MDO operation.
HYS
3
3
The HYS bit has no effect on MDO operation.
SRC WPE
4
4
The WPE bit should be set to zero for MDO operation.
WPS
W
Reset
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
= Unimplemented or Reserved
Table 16-66. SIU_PCR75 PA values
Signal Name Module Description I/O
1,2
PA value
Primary MDO[4] Nexus Message data out O 0b01
ALT1 ETPU_A[2] eTPU eTPU channel O 0b10
GPIO GPIO[75] SIU GPIO I/O 0b00