NXP Semiconductors MPC5644A, Reference Manual, Page: 332 / 1735

External Bus Interface (EBI)
MPC5644A Microcontroller Reference Manual, Rev. 6
332 Freescale Semiconductor
with OE negated and CS asserted, to allow for the memory to three-state the bus prior to the EBI driving
the address on the next clock. This clock gap already exists (for other reasons) for non-small-access
transfers, so no additional clock gap is inserted for those cases. See
Figure 14-37 for an example of a small
access read with A/D multiplexing enabled.
In general, timing diagrams in A/D multiplexing mode are very similar to other diagrams in this document
(including support for Burst accesses), except for the behavior of the ADDR and DATA busses, which can
be seen in
Figure 14-37 .
Figure 14-37. Small access (32-bit read to 16-bit port) on Address/Data multiplexed bus
CLKOUT
*ADDR[3:31]
TS
**DATA[16:31]
TA
RD_WR
DATA is valid
BDIP
OE
CSx
DATA is valid
Addr Addr+0x2
Addr Addr+0x2
Clock Gap
* While the EBI drives all of ADDR[3:31] to valid address, typically only ADDR[3:15] (or less) are used in the
system, as DATA[16:31] (or DATA[0:15]) would be used for address and data on an external muxed device.
** Or DATA[0:15], based on D16_31 bit in EBI_MCR.