NXP Semiconductors MPC5644A, Reference Manual, Page: 228 / 1735

Flash memory
MPC5644A Microcontroller Reference Manual, Rev. 6
228 Freescale Semiconductor
If the user attempts to write two or more MCR bits simultaneously then only the bit with the lowest priority
level is written. Setting two bits with the same priority level is prevented by existing write locks or do not
put the flash in an illegal state.
For example, setting ERS and PGM simultaneously results in only ERS being set. Attempting to clear
EHV while setting PSUS results in EHV being cleared, while PSUS is unaffected.
12.3.2.2 Low/Mid-Address Space Block Lock Register (LMLR)
The Low/Mid-Address Space Block Lock Register (LMLR) provides a means to protect blocks from being
modified. These bits, along with the SLLOCK bits in the SLMLR, determine if the block is locked from
program or erase. An “OR” of LMLR and SLMLR determines the final lock status.
NOTE
A reset value of 1* in Figure 12-4 indicates that the reset value of these
registers is determined by Flash values in the shadow block. An erased
shadow block causes the reset value to be 1.
3 EHV
4 ESUS, PSUS
Offset 0x0004 Access: User read/write
R
LME 0 0 0 0 0 0 0 0 0 0 SLOCK 0 0 MLOCK
W
Reset
0 0 0 0 0 0 0 0 0 0 0 X 0 0 X X
R
0 0 0 0 0 0 LLOCK
W
Reset
0 0 0 0 0 0
1* 1* 1* 1* 1* 1* 1* 1* 1* 1*
= Unimplemented or Reserved
Figure 12-4. Low/Mid-Address Space Block Lock Register (LMLR)
Table 12-6. LMLR field descriptions
Field Description
LME Low/Mid-Address Lock Enable
The LME bit is used to enable the Lock fields (SLOCK, MLOCK and LLOCK) to be set or cleared by
register writes. LME is a status bit only, and may not be written or cleared, and the reset value is 0. The
method to set LME is to write a password, and if the password matches, LME is set to reflect the status
of enabled, and is enabled until a reset operation occurs. For LME, the password 0xA1A1_1111 must
be written to the LMLR.
0: Low/Mid-Address Locks are disabled, and can not be modified.
1: Low/Mid-Address Locks are enabled to be written.
Table 12-5. MCR bit set/clear priority levels
Priority level MCR bit(s)