NXP Semiconductors MPC5644A, Reference Manual, Page: 216 / 1735

General-Purpose Static RAM (SRAM)
MPC5644A Microcontroller Reference Manual, Rev. 6
216 Freescale Semiconductor
If the system SRAM is cached, cache lines can retain indeterminate data that is not written to memory
unless the region is set for write-through mode.
NOTE
Standby memory can contain the previous data values if a reset occurs while
cache is running in copy back mode.
11.9 Initialization and application information
To use the SRAM, the ECC must check all bits that require initialization after power on. Use either a 32-bit
or 64-bit cache-inhibited write to each SRAM location to initialize the SRAM array as part of the
application initialization code. All writes must specify an even number of registers performed on 32-bit or
64-bit word-aligned boundaries respectively. If the write is not the entire 32 bits (8 or 16 bits), a
read/modify/write operation is generated that checks the ECC value upon the read. See
Section 11.8,
SRAm ecc mechanism .
NOTE
You must initialize SRAM, even if the application does not use ECC
reporting.
11.9.1 Example code
To initialize SRAM correctly, use a store multiple word ( stmw) instruction to implement 64-bit writes to
all SRAM locations. The stmw instruction concatenates two 32-bit registers to implement a single 64-bit
write. To ensure the writes are 64 bits, specify an even number of registers and write on 64-bit
word-aligned boundaries.
The following example code illustrates the use of the stmw instruction to initialize the SRAM ECC bits.
init_RAM:
lis r11,0x4000 # base address of the SRAM, 64-bit word aligned
ori r11,r11,0 # not needed for this address but could be for others
li r12,1536 # loop counter to get all of SRAM;
# 192*1024/4 bytes/32 GPRs =1536
mtctr r12
init_ram_loop:
stmw r0,0(r11) # write all 32 GPRs to SRAM
addi r11,r11,128 # inc the ram ptr; 32 GPRs * 4 bytes = 128
bdnz init_ram_loop # loop for 192K of SRAM
blr # done