NXP Semiconductors MPC5644A, Reference Manual, Page: 215 / 1735

General-Purpose Static RAM (SRAM)
MPC5644A Microcontroller Reference Manual, Rev. 6
Freescale Semiconductor 215
If the entire 32 data bits are written to SRAM, no read operation is performed and the ECC is calculated
across the 32 bits of data. The 7-bit ECC is appended to the data segment and written to SRAM. If the write
operation is less than the entire 32-bit data width (1- or 2-byte segment), the following occurs:
1. The ECC mechanism checks the entire 32 bits of data for errors, detecting and either correcting or
flagging errors.
2. The write data bytes (1- or 2-byte segment) are merged with the corrected 32 bits on the data bus.
3. The ECC is then calculated on the resulting 32 bits formed in the previous step.
4. The 7-bit ECC result is appended to the 32 bits from the data, and the 39-bit value is then written
to SRAM.
11.8.1 Access timing
The system bus is a two stage pipelined bus, which makes the timing of any access dependent on the access
during the previous clock.
Table 11-2 shows the wait states for accesses, current is the access being
measured, previous is the RAM access during the previous clock.
11.8.2 Reset effects on SRAM accesses
If a reset event asserts during a read or write operation to SRAM, the completion of that access depends
on the cycle at which the reset occurs. Data read from or written to SRAM before the reset event occurred
is retained, and no other address locations are accessed or changed.
Table 11-2. Number of wait states required for RAM operation
Current operation Previous operation Number of wait states
Read
Idle 0
1
/ 1
2
1
Applies if additional SRAM read wait state in ECSM_MUDCR is disabled
2
Applies if additional SRAM read wait state in ECSM_MUDCR is enabled
Read 0
1
/ 1
2
32 or 64-bit write 0
1
/ 1
2
8 or 16-bit write 1
1
/ 2
2
32 or 64-bit write
Idle 0
Read 0
32 or 64-bit write 0
8 or 16-bit write 1
8 or 16-bit write
Idle 0
Read 0
32 or 64-bit write 0
8 or 16-bit write 1