NXP Semiconductors MPC5644A, Reference Manual, Page: 209 / 1735

Peripheral Bridge (PBRIDGE)
MPC5644A Microcontroller Reference Manual, Rev. 6
Freescale Semiconductor 209
10.6.2.2 Peripheral access control registers (PACR)
Each PACR register contains one or more 4-bit fields, called PACR n , as shown in Table 10-2 . Each of
these fields defines the access levels supported by the associated module. The lists of modules and their
corresponding numbers are shown in
Table 10-6 .
Each PACR n field has the structure described in Figure 10-3 and Table 10-5 .
Figure 10-3. PACRn field structure
0 1 2 3
R 0 SP WP TP
W
Reset
0 1 0 0
Table 10-5. PACRn field structure descriptions
Subfield Description
SP Supervisor Protect
This bit determines whether the peripheral requires supervisor privilege level for access.
0 This peripheral does not require supervisor privilege level for accesses.
1 This peripheral requires supervisor privilege level for accesses. The MPCRx[MPL] control bit for
the master must be set. If not, the access is terminated with an error response and no peripheral
access is initiated on the IPS bus.
WP Write Protect
This bit determines whether the peripheral allows write accesses.
0 This peripheral allows write accesses.
1 This peripheral is write protected. If a write access is attempted, the access is terminated with an
error response and no peripheral access is initiated on the IPS bus.
TP Trusted Protect
This bit determines whether the peripheral allows accesses from an untrusted master.
0 Accesses from an untrusted master are allowed.
1 Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted
master, the access is terminated with an error response and no peripheral access is initiated on the
IPS bus.
Table 10-6. Peripheral Access Control Register (PACR) fields
Register Peripheral Reset value
PACR 1 Crossbar 0100b, meaning
SP = 1
WP = 0
TP = 0
PACR 4 MPU
PACR 14 SWT
PACR 15 STM
PACR 16 ECSM
PACR 17 DMA
PACR 18 Interrupt controller