NXP Semiconductors MPC5644A, Reference Manual, Page: 1696 / 1735

Development Trigger Semaphore (DTS)
MPC5644A Microcontroller Reference Manual, Rev. 6
1696 Freescale Semiconductor
NOTE
The XBAR Master ID should not be confused with the Master Port number
of the XBAR. See
Chapter 9, Multi-Layer AHB Crossbar Switch (XBAR) ,
for details.
Tools must access the DTS registers (DTS_ENABLE, DTS_STARTUP, and DTS_SEMAPHORE)
through the Nexus Read/Write Access mechanism of the e200z4 core. JTAG accesses through either core
appear as if the access is via the core and therefore will not have the same level of access as a Nexus R/W
access.
38.4 Memory map
Table 38-2 shows the memory map of the Development Trigger Semaphore module registers. Three 32-bit
registers are implemented. The rest of the memory map (0xC3F9_C00C through 0xC3F9_FFFF) is
reserved.
38.5 Register descriptions
38.5.1 DTS Output Enable Register (DTS_ENABLE)
This DTS_ENABLE register controls the DTS Trigger Output (DTO) and whether DTO is active on the
EVTO output pin of the device.
Figure 38-4 shows the format of the DTS_ENABLE register.
NOTE
Access to the DTS_SEMAPHORE and DTS_STARTUP registers are
unaffected by the state of this register.
Table 38-2. DTS Module
Address Register Description Size (bits) Access
DTS_BASE (0xC3F9_C000) DTS_ENABLE DTS output enable register 32 Restricted R/W
1
1
Only certain types of accesses are allowed. See separate description.
DT 0x0004 DTS_STARTUP DTS startup register 32 Restricted R/W
1
DT 0x0008 DTS_SEMAPHORE DTS semaphore register 32 Restricted R/W
1
DT 0x000C –
DT 0xFFFF Reserved