NXP Semiconductors MPC5644A, Reference Manual, Page: 1695 / 1735

Development Trigger Semaphore (DTS)
MPC5644A Microcontroller Reference Manual, Rev. 6
Freescale Semiconductor 1695
DTS_SEMAPHORE register
1
. Similarly, the DTS_ENABLE and DTS_STARTUP registers can only be
written via a Nexus Read/Write Access.
NOTE
Nexus Read/Write Accesses use the load/store bus of the core to perform
accesses, but Nexus accesses have a different Master ID than normal core
load/stores.
Figure 38-3. DTS device connections
38.3.1 DTS register access
A summary of accesses to all DTS registers by bus masters is provided in Table 38-1 . Note that only proper
32-bit accesses are valid. The effect of write accesses, that are not 32 bits, is not defined.
Access to DTS module registers is controlled based on the XBAR Master ID of the accessing module. The
table below shows the XBAR Master IDs for each of port.
1. DTS_SEMAPHORE bits are cleared automatically when read through the Nexus/JTAG port.
Table 38-1. DTS register access effects
Register
32-bit Read 32-bit Write
RWA
1
1
Nexus Read/Write access via an external tool.
e200z4 eDMA FlexRay RWA
1
e200z4 eDMA FlexRay
DTS_ENABLE Data Data Data Data Data No effect No effect No effect
DTS_STARTUP Data Data Data Data Data No effect No effect No effect
DTS_SEMAPHORE Data and
Clear
2
2
A read of the DTS_SEMAPHORE register by either Nexus Read/Write Access module is destructive and clears all
bits in the register.
Data Data Data No effect Bit OR Bit OR No effect
eDMA
FlexRay
X
BAR
PB
R
IDGE
XBAR Slave Port
XBAR Master ID
DTS
Peripheral Bus
XBAR Master ID
e200z4
DTS Trigger Output
EVTO Pin
(DTO)
EBI
NPC
EV
T
O
In
put
s