NXP Semiconductors MPC5644A, Reference Manual, Page: 1685 / 1735

Nexus Port Controller (NPC)
MPC5644A Microcontroller Reference Manual, Rev. 6
Freescale Semiconductor 1685
Figure 37-7. Transmission sequence of messages
37.5.3 IEEE 1149.1-2001 (JTAG) TAP
The NPC block uses the IEEE 1149.1-2001 TAP for accessing registers. Each of the individual Nexus
blocks on the device implements a TAP controller for accessing its registers as well. TAP signals include
TCK, TDI, TMS, and TDO. There may also be other blocks on the MCU that use the TAP and implement
a TAP controller. The value of the JCOMP input controls ownership of the port between Nexus and
non-Nexus blocks sharing the TAP.
Refer to the IEEE 1149.1-2001 specification for further detail on electrical and pin protocol compliance
requirements.
The NPC implements a Nexus controller state machine that transitions based on the state of the IEEE
1149.1-2001 state machine shown in
Figure 37-9 . The Nexus controller state machine is defined by the
IEEE-ISTO 5001-2010 standard. It is shown in Figure 37-10 .
The instructions implemented by the NPC TAP controller are listed in Table 37-10 . The value of the
NEXUS-ENABLE instruction is 0b0000. Each unimplemented instruction acts like the BYPASS
instruction. The size of the NPC instruction register is 4-bits.
Data is shifted between TDI and TDO starting with the least significant bit as illustrated in Figure 37-8 .
This applies for the instruction register and all Nexus tool-mapped registers.
Figure 37-8. Shifting data into register
Table 37-10. Implemented instructions
Instruction name Private/Public Opcode Description
NEXUS-ENABLE public 0x0 Activate Nexus controller state machine to read and write NPC
registers.
BYPASS private 0xF NPC BYPASS instruction. Also the value loaded into the NPC
IR upon exit of reset.
TCODE (6 bits) FIELD #1
FIELD #2
1 2 3
msb lsb msb lsb msb lsb
Selected Register
MSB LSB
TDI TDO