NXP Semiconductors MPC5644A, Reference Manual, Page: 1661 / 1735

JTAG Controller (JTAGC)
MPC5644A Microcontroller Reference Manual, Rev. 6
Freescale Semiconductor 1661
36.3.2.5 JCOMP—JTAG compliancy
The JCOMP signal provides IEEE 1149.1-2001 compatibility and provides the ability to share the TAP.
The JTAGC TAP controller is enabled when JCOMP is set to the JTAGC enable encoding, otherwise the
JTAGC TAP controller remains in reset.
36.4 Register definition
This section provides a detailed description of the JTAGC block registers accessible through the TAP
interface, including data registers and the instruction register. Individual bit-level descriptions and reset
states of each register are included. These registers are not memory-mapped and can only be accessed
through the TAP.
36.4.1 Register descriptions
The JTAGC block registers are described in this section.
36.4.1.1 Instruction Register
The JTAGC block uses a 5-bit instruction register as shown in Table 36-2 . The instruction register allows
instructions to be loaded into the block to select the test to be performed or the test data register to be
accessed or both. Instructions are shifted in through TDI while the TAP controller is in the Shift-IR state,
and latched on the falling edge of TCK in the Update-IR state. The latched instruction value can only be
changed in the Update-IR and Test-Logic-Reset TAP controller states. Synchronous entry into the
Test-Logic-Reset state results in the IDCODE instruction being loaded on the falling edge of TCK.
Asynchronous entry into the Test-Logic-Reset state results in asynchronous loading of the IDCODE
instruction. During the Capture-IR TAP controller state, the instruction shift register is loaded with the
value 0b10101, making this value the register’s read value when the TAP controller is sequenced into the
Shift-IR state.
Figure 36-2. 5-bit Instruction Register
36.4.1.2 Bypass Register
The bypass register is a single-bit shift register path selected for serial data transfer between TDI and TDO
when the BYPASS, CLAMP, HIGHZ or reserve instructions are active. After entry into the Capture-DR
state, the single-bit shift register is set to a logic 0. Therefore, the first bit shifted out after selecting the
bypass register is always a logic 0.
4 3 2 1 0
R 1 0 1 0 1
W Instruction Code
Reset: 0 0 0 0 1