NXP Semiconductors MPC5644A, Reference Manual, Page: 1660 / 1735

JTAG Controller (JTAGC)
MPC5644A Microcontroller Reference Manual, Rev. 6
1660 Freescale Semiconductor
36.3 External signal description
36.3.1 Overview
The JTAGC consists of five signals that connect to off chip development tools and allow access to test
support functions. The JTAGC signals are outlined in
Table 36-4 .
36.3.2 Detailed signal descriptions
This section describes each of the signals listed in Table 36-4 in more detail.
36.3.2.1 TCK—Test Clock Input
Test Clock Input (TCK) is an input pin used to synchronize the test logic and control register access
through the TAP.
36.3.2.2 TDI—Test Data Input
Test Data Input (TDI) is an input pin that receives serial test instructions and data. TDI is sampled on the
rising edge of TCK.
36.3.2.3 TDO—Test Data Output
Test Data Output (TDO) is an output pin that transmits serial output for test instructions and data. TDO is
three-stateable and is actively driven only in the Shift-IR and Shift-DR states of the TAP controller state
machine, which is described in
Section 36.5.3, TAP controller state machine . The TDO output of this block
is clocked on the falling edge of TCK and sampled by the development tool on the rising edge of TCK.
36.3.2.4 TMS—Test Mode Select
Test Mode Select (TMS) is an input pin used to sequence the IEEE 1149.1-2001 test control state machine.
TMS is sampled on the rising edge of TCK.
Table 36-4. JTAG signal properties
Name I/O Function Reset state Pull
1
1
The pull is not implemented in this block. Pullup/pulldown devices are implemented in the pads.
TCK Input Test Clock — Down
TDI Input Test Data In — Up
TDO Output Test Data Out High Z
2
2
TDO output buffer enable is negated when the JTAGC is not in the Shift-IR or Shift-DR states. A
weak pull may be implemented at the TDO pad for use when JTAGC is inactive.
—
TMS Input Test Mode Select — Up
JCOMP Input JTAG Compliancy — Down