NXP Semiconductors MPC5644A, Reference Manual, Page: 1658 / 1735

JTAG Controller (JTAGC)
MPC5644A Microcontroller Reference Manual, Rev. 6
1658 Freescale Semiconductor
36.2 Introduction
Figure 36-1 is a block diagram of the JTAG Controller (JTAGC) block.
Figure 36-1. JTAG STL (IEEE 1149.1) block diagram
36.2.1 Overview
The JTAGC block provides the means to test chip functionality and connectivity while remaining
transparent to system logic when not in test mode. Testing is performed via a boundary scan technique, as
defined in the IEEE 1149.1-2001 standard. All data input to and output from the JTAGC block is
communicated in serial format.
36.2.2 Features
The JTAGC block is compliant with the IEEE 1149.1-2001 standard, and supports the following features:
• IEEE 1149.1-2001 Test Access Port (TAP) interface
— 4 pins (TDI, TMS, TCK, and TDO)
• JCOMP input that provides reset control and the ability to share the TAP
TCK
TMS
TDI
Test Access Port (TAP)
TDO
32-bit Device Identification Register
Boundary Scan Register
.
.
Controller
1-bit Bypass Register
.
5-bit TAP Instruction Decoder
5-bit TAP Instruction Register
.
.
.
JCOMP
5-bit TAP Instruction Decoder .