Power Management Controller (PMC)
MPC5644A Microcontroller Reference Manual, Rev. 6
Freescale Semiconductor
1639
35.3.1
Module Configuration Register (MCR)
The configuration register contains configuration and reset and interrupt enable bits for the LVI monitors.
Please note that in the MPC5644A devices the LVI reset is equivalent to a POR. After an LVI reset, bit
SIU_RSR[PORS] is set and the PMC_SR is reset—no LVI event information is retained. To enable
application to report an LVI event, disable the reset using the appropriate field, i.e., LVRER or LVREH,
and enable the interrupt for the LVI using its interrupt enable field, e.g., LVIER. You must make sure that
the ISR will be finished before the voltage sinks below its functional specification and this may require an
increase in the LVI level.
The software system reset and the POR/LVI reset are handled differently by the device. See
for more details. After a software system reset different status flags are set in the
SIU_RSR register.
NOTE
LVI resets and interrupts are only enabled when the voltage regulator is
enabled (VDDREG = 5 V). If the user grounds VDDREG
(VDDREG = 0 V) and supplies the voltages externally (1.2 V and 3.3 V), it
is also necessary to provide the LVI monitoring externally.
Table 35-2. Power management controller memory map
Address
Register
Location
PMC_BASE (0XC3FB_C000)
+ 0x0000
MCR — Module Configuration Register
PMC_BASE (0XC3FB_C000)
+ 0x0004
TRIMR — Trimming Register
PMC_BASE (0XC3FB_C000)
+ 0x0008
SR — Status Register
Offset: PM 0x0000
Access: User read/write
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
R
LV
R
E
R
LV
R
E
H
LV
R
E
5
0
LV
R
E
3
3
LV
R
E
C
0
0
0
LV
IE
R
LV
IE
H
LV
IE
5
0
LV
IE
3
3
LV
IC
0
0
TL
K
W
Reset
1
0
0
1
1
0
0
0
0
0
0
0
0
0
0
0
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
R
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
W
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Figure 35-3. Module Configuration Register (MCR)
Summary of Contents for MPC5644A
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