NXP Semiconductors MPC5644A, Reference Manual, Page: 1610 / 1735

FlexRay Communication Controller (FlexRay)
MPC5644A Microcontroller Reference Manual, Rev. 6
1610 Freescale Semiconductor
33.6.24.2 Memory error reporting
The memory error reporting is enabled only if the ECC functionality enable bit ECCE in the Module
Configuration Register (FR_MCR) is set.
For each of the two memories exists two sets of internal registers to store the detection of one corrected
and one non-corrected memory error.
If a memory error is detected, the module checks whether the related error interrupt flag in the ECC Error
Interrupt Flag and Enable Register (FR_EEIFER) is set.
• If the error interrupt flag is set, the related internal error reporting register is not updated and the
related error overflow flag is set to 1 to indicate a loss of error condition.
• If the error interrupt flag is not set, the internal reporting register is updated and the error interrupt
flag is set to 1. If two or more memory errors of the same type are detected, the error for the bank
with the lower bank number will be reported, and the error overflow flag will be set to 1.
If a memory error is detected for at least two banks of one memory, the related error overflow flag is set
to 1 to indicate a loss of error condition.
33.6.24.2.1 PE DRAM checkbits
The coding of the checkbits reported in ECC Error Report Code Register (FR_EERCR) for PE DRAM
memory errors is shown in Table 33-132 . This table shows the implemented enhanced Hamming code. If
the error injection was applied to distort the checkbits, then the distorted checkbits are reported.
Table 33-130. Detected memory error types
Memory Priority Memory data Indication
CHI LRAM 0 (highest) All zero’s No Error – Valid Data
PE DRAM Non-Corrected Error
CHI LRAM All one’s Non-Corrected Error
PE DRAM
CHI LRAM 1 (lowest) One bit flipped Non-Corrected Error
PE DRAM Corrected Error
CHI LRAM Two bits flipped Non-Corrected Error
PE DRAM
CHI LRAM Three or more bits flipped One out of {No error, Non-Corrected Error}, defined by
coding given in
Section 33.6.24.2.3, CHI LRAM checkbits ”
and Section 33.6.24.2.3, CHI LRAM checkbits ”
PE DRAM One out of {No error, Corrected Error, Non-Corrected Error},
defined by coding given in
Section 33.6.24.2.1, PE DRAM
checkbits ” and Section 33.6.24.2.2, PE DRAM syndrome ”