NXP Semiconductors MPC5644A, Reference Manual, Page: 1608 / 1735

FlexRay Communication Controller (FlexRay)
MPC5644A Microcontroller Reference Manual, Rev. 6
1608 Freescale Semiconductor
33.6.22.1 PE DRAM read access
A read access from the PE DRAM can be initiated in any protocol state. The following sequence describes
a read access from the PE DRAM address 0x70.
1. FR_PEDRAR = 0x00E0; // INST = 0x0; ADDR = 070
2. wait until FR_PEDRAR[DAD] == 1; // wait for end of PE DRAM access
3. val = FR_PEDRDR[DATA]; // get read PE DRAM data
The read access is handled by the PE internal CPU with the lowest execution priority. This may cause an
response delay with a maximum of 1000 PE clock cycle (25µs).
33.6.22.2 PE DRAM write access
A write access into the PE DRAM can be initiated in any protocol state. The following sequence describes
a write access to the PE DRAM address 0x70.
1. FR_PEDRAR = 0x30E0; // INST = 0x3; ADDR = 0x70
2. wait until FR_PEDRAR[DAD] == 1; // wait for end of PE DRAM access
3. val = FR_PEDRDR[DATA]; // get read back PE DRAM data
The write access is handled by the PE internal CPU with the lowest execution priority. This may causes
an response delay with a maximum of 1000 PE clock cycle (25µs).
If the conditions given in Section 33.6.22.3, PE DRAM write access limitations ” are fulfilled, the data
provided in PE DRAM Data Register (FR_PEDRDR) are written into the PE DRAM, read back in the next
clock cycle and stored into the PE DRAM Data Register (FR_PEDRDR) . Otherwise, data are not written
into the PE DRAM and 0x0000 is stored into the PE DRAM Data Register (FR_PEDRDR) .
33.6.22.3 PE DRAM write access limitations
The PE DRAM is used by the protocol engine if the module is not in POC:default config state. The only
address not used by the protocol engine is 0x70. To prevent the corruption of protocol engine data the
following PE DRAM write access limitations apply for application writes.
1. When the module is in POC:default config state, all PE DRAM addresses are writable.
2. When the module is not in POC:default config state, only PE DRAM address 0x70 is writable.
33.6.23 CHI lookup-table memory (CHI LRAM)
The CHI Lookup-Table Memory (CHI LRAM) is an CHI internal memory which contains the message
buffer configuration data. The configuration data for two message buffers are contained in one memory
row. The CHI LRAM is divided into six memory banks.