NXP Semiconductors MPC5644A, Reference Manual, Page: 1581 / 1735

FlexRay Communication Controller (FlexRay)
MPC5644A Microcontroller Reference Manual, Rev. 6
Freescale Semiconductor 1581
33.6.8.1.2 Buffer type not changed (RC2)
A reconfiguration will not change the buffer type of the individual message buffer if the message buffer
buffer type bit FR_MBCCSRn[MBT] is not changed. This type of reconfiguration is denoted by RC2 in
Figure 33-147 . It applies only to single transmit and receive message buffers. Single transmit and receive
message buffers can be RC2-reconfigured when in the HDis or HDisLck state.
33.6.8.1.3 Buffer type changed (RC3)
A reconfiguration will change the buffer type of the individual message buffer if the message buffer type
bit FR_MBCCSRn[MBT] is changed. This type of reconfiguration is denoted by RC3 in
Figure 33-147 .
The RC3 reconfiguration splits one double buffer into two single buffers or combines two single buffer
into one double buffer. In the later case, the two single message buffers must have consecutive message
buffer numbers and the smaller one must be even. Message Buffers can be RC3 reconfigured if they are in
the HDis state.
Figure 33-147. Message buffer reconfiguration scheme
33.6.9 Receive FIFOs
This section provides the functional description of the two receive FIFOs.
33.6.9.1 Overview
The two receive FIFOs implement the queued message buffer concept defined by the FlexRay
Communications System Protocol Specification, Version 2.1 Rev A. One FIFO is assigned to channel A,
the other FIFO is assigned to channel B. Both FIFOs work completely independent from each other.
The message buffer structure of each FIFO is described in Section 33.6.3.3, Receive FIFO”. The area in
the FlexRay memory area for each of the two FIFOs is characterized by:
• The FIFO system memory base address
• The index of the first FIFO entry given by Receive FIFO Start Index Register (FR_RFSIR)
• The number of FIFO entries and the length of each FIFO entry as given by Receive FIFO Depth
and Size Register (RFDSR)
single RX single TX
double TX (commit side)
double TX (transmit side)
RC1
RC1
RC1
RC2
RC3 RC3