NXP Semiconductors MPC5644A, Reference Manual, Page: 1489 / 1735

FlexRay Communication Controller (FlexRay)
MPC5644A Microcontroller Reference Manual, Rev. 6
Freescale Semiconductor 1489
If the application has locked the odd synchronization table at the end of the
static segment of an odd communication cycle, the CC will not update the
values SFODB and SFODA.
33.5.2.34 Sync Frame Table Offset Register (FR_SFTOR)
This register defines the FlexRay memory area related offset for sync frame tables. For more details, see
Section 33.6.12, Sync frame ID and sync frame deviation tables” .
Table 33-38. FR_SFCNTR field description
Field Description
SFEVB Sync Frames Channel B, even cycle — protocol related variable: size of ( vsSyncIdListB for even cycle)
This field provides the size of the internal list of frame IDs of received synchronization frames used for
clock synchronization.
SFEVB Sync Frames Channel A, even cycle — protocol related variable: size of ( vsSyncIdListA for even cycle)
This field provides the size of the internal list of frame IDs of received synchronization frames used for
clock synchronization.
SFODB Sync Frames Channel B, odd cycle — protocol related variable: size of ( vsSyncIdListB for odd cycle)
This field provides the size of the internal list of frame IDs of received synchronization frames used for
clock synchronization.
SFODA Sync Frames Channel A, odd cycle — protocol related variable: size of ( vsSyncIdListA for odd cycle)
This field provides the size of the internal list of frame IDs of received synchronization frames used for
clock synchronization.
Base + 0x0042 Write: POC:config
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
R
SFT_OFFSET[15:1]
0
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Figure 33-34. Sync Frame Table Offset Register (FR_SFTOR)
Table 33-39. FR_SFTOR Field Description
Field Description
SFT_OFFSET Sync Frame Table Offset — The offset of the Sync Frame Tables in the FlexRay memory area. This
offset is required to be 16-bit aligned. Thus STF_OFFSET[0] is always 0.