NXP Semiconductors MPC5644A, Reference Manual, Page: 1438 / 1735

FlexCAN Module
MPC5644A Microcontroller Reference Manual, Rev. 6
1438 Freescale Semiconductor
The clock source (CLKSRC bit) should be selected while the module is in Disable Mode. After the clock
source is selected and the module is enabled (MDIS bit negated), FlexCAN automatically goes to Freeze
Mode. In Freeze Mode, FlexCAN is unsynchronized to the CAN bus, the HALT and FRZ bits in the MCR
are set, the internal state machines are disabled and the FRZACK and NOTRDY bits in the MCR are set.
The Tx pin is in recessive state and FlexCAN does not initiate any transmission or reception of CAN
frames. Note that the Message Buffers and the Rx Individual Mask Registers are not affected by reset, so
they are not automatically initialized.
For any configuration change/initialization it is required that FlexCAN is put into Freeze Mode (see
Section 32.5.9.1, Freeze Mode ). The following is a generic initialization sequence applicable to the
FlexCAN module:
• Initialize the Module Configuration Register (MCR)
— Enable the individual filtering per message buffer and reception queue features by setting the
MBFEN bit
— Enable the warning interrupts by setting the WRNEN bit
— If required, disable frame self reception by setting the SRX_DIS bit
— Enable the FIFO by setting the FEN bit
— Enable the abort mechanism by setting the AEN bit
— Enable the local priority feature by setting the LPRIO_EN bit
• Initialize the Control Register (CR)
— Determine the bit timing parameters: PROPSEG, PSEG1, PSEG2, RJW
— Determine the bit rate by programming the PRESDIV field
— Determine the internal arbitration mode (bit CR[LBUF])
• Initialize the Message Buffers
— The Control and Status word of all Message Buffers must be initialized
— If FIFO was enabled, the 8-entry ID table must be initialized
— Other entries in each Message Buffer should be initialized as required
• Initialize the Rx Individual Mask Registers
• Set required interrupt mask bits in the corresponding IMRL or IMRH register (for all message
buffer interrupts), in the CR (for Bus Off and Error interrupts) and in the MCR for Wake-Up
interrupt
• Negate the HALT bit in MCR
Starting with the last event, FlexCAN attempts to synchronize to the CAN bus.
32.6.2 FlexCAN addressing and RAM size configurations
There are three RAM configurations that can be implemented within the FlexCAN module. The possible
configurations are:
• For 16 message buffers: 288 bytes for message buffer memory and 64 bytes for Individual Mask
Registers