NXP Semiconductors MPC5644A, Reference Manual, Page: 1434 / 1735

FlexCAN Module
MPC5644A Microcontroller Reference Manual, Rev. 6
1434 Freescale Semiconductor
A direct consequence of the first requirement is that the minimum number of time quanta per CAN bit must
be 8, so the oscillator clock frequency should be at least 8 times the CAN bit rate. The minimum frequency
ratio specified in
Table 32-21 can be achieved by choosing a high enough peripheral clock frequency when
compared to the oscillator clock frequency, or by adjusting one or more of the bit timing parameters
(PRESDIV, PROPSEG, PSEG1, PSEG2). As an example, taking the case of 64 message buffers, if the
oscillator and peripheral clock frequencies are equal and the CAN bit timing is programmed to have 8 time
quanta per bit, then the prescaler factor (P 1) should be at least 2. For prescaler factor equal to
one and CAN bit timing with 8 time quanta per bit, the ratio between peripheral and oscillator clock
frequencies should be at least 2.
32.5.9 Modes of operation details
32.5.9.1 Freeze Mode
This mode is entered by asserting MCR[HALT] or when the MCU is put into Debug Mode. In both cases
it is also necessary that MCR[FRZ] is asserted and the module is not in either of the low power modes
(Disable or Stop). When Freeze Mode is requested during transmission or reception, FlexCAN does the
following:
• Waits to be in either Intermission, Passive Error, Bus Off or Idle state
• Waits for all internal activities like arbitration, matching, move-in and move-out to finish
• Ignores the Rx input pin and drives the Tx pin as recessive
• Stops the prescaler, thus halting all CAN protocol activities
• Grants write access to the Error Counters Register, which is read-only in other modes
• Sets the NOTRDY and FRZACK bits in MCR
After requesting Freeze Mode, the user must wait for MCR[FRZACK] to be asserted before executing any
other action, otherwise FlexCAN may operate in an unpredictable way. In Freeze mode, all memory
mapped registers are accessible.
Exiting Freeze Mode is done in one of the following ways:
• CPU negates MCR[FRZ ]
• The MCU is removed from Debug Mode and/or the HALT bit is negated
Once out of Freeze Mode, FlexCAN tries to resynchronize to the CAN bus by waiting for 11 consecutive
recessive bits.
Table 32-21. Minimum Ratio Between Peripheral Clock Frequency and CAN Bit Rate
Number of Message Buffers Minimum Ratio
16 8
32 8
64 16