NXP Semiconductors MPC5644A, Reference Manual, Page: 1312 / 1735

Deserial Serial Peripheral Interface (DSPI)
MPC5644A Microcontroller Reference Manual, Rev. 6
1312 Freescale Semiconductor
When the CONT bit = 0, the DSPI drives the asserted Chip Select signals to their idle states in between
frames. The idle states of the Chip Select signals are selected by the PCSISn bits in the DSPI_MCR.
Figure 30-46 shows the timing diagram for two 4-bit transfers with CPHA = 1 and CONT = 0.
Figure 30-46. Example of non-continuous format (CPHA = 1, CONT = 0)
When the CONT bit = 1, the PCS signal remains asserted for the duration of the two transfers. The Delay
between Transfers (t
DT)
is not inserted between the transfers. Figure 30-47 shows the timing diagram for
two 4-bit transfers with CPHA = 1 and CONT = 1.
Figure 30-47. Example of continuous transfer (CPHA = 1, CONT = 1)
When using DSPI with continuous selection follow these rules:
t
CSC
t
DT
t
CSC
SCK
PCSx
SCK
Master SOUT
Master SIN
t
CSC
= PCS to SCK delay
t
DT
= Delay after Transfer (minimum CS negation time)
(CPOL = 0)
(CPOL = 1)
t
ASC
t
ASC
= After SCK delay
t
CSC
t
CSC
SCK
PCS
SCK
Master SOUT
Master SIN
t
CSC
= PCS to SCK delay
(CPOL = 0)
(CPOL = 1)
t
ASC
t
ASC
= After SCK delay