NXP Semiconductors MPC5644A, Reference Manual, Page: 1294 / 1735

Deserial Serial Peripheral Interface (DSPI)
MPC5644A Microcontroller Reference Manual, Rev. 6
1294 Freescale Semiconductor
time the DSPI_POPR is read. The maximum value of the field is equal to DSPI_HCR[RXFR] and it rolls
over after reaching the maximum.
30.9.2.5.1 Filling the RX FIFO
The RX FIFO is filled with the received SPI data from the shift register. While the RX FIFO is not full,
SPI frames from the shift register are transferred to the RX FIFO. Every time a SPI frame is transferred to
the RX FIFO the RX FIFO Counter is incremented by one.
If the RX FIFO and shift register are full and a transfer is initiated, the RFOF bit in the DSPI_SR is set
indicating an overflow condition. Depending on the state of the ROOE bit in the DSPI_MCR, the data from
the transfer that generated the overflow is either ignored or shifted in to the shift register. If the ROOE bit
is set, the incoming data is shifted in to the shift register. If the ROOE bit is cleared, the incoming data is
ignored.
30.9.2.5.2 Draining the RX FIFO
Host CPU or a DMA can remove (pop) entries from the RX FIFO by reading the DSPI POP RX FIFO
Register (DSPI_POPR). A read of the DSPI_POPR decrements the RX FIFO Counter by one. Attempts to
pop data from an empty RX FIFO are ignored and the RX FIFO Counter remains unchanged. The data,
read from the empty RX FIFO, is undetermined.
When the RX FIFO is not empty, the RX FIFO Drain Flag (RFDF) in the DSPI_SR is set. The RFDF bit
is cleared when the RX_FIFO is empty and the DMA controller indicates that a read from DSPI_POPR is
complete or by writing a ‘1’ to it.
30.9.3 Deserial serial interface (DSI) configuration
The DSI configuration supports pin count reduction by serializing Parallel Input signals or register bits and
shifting them out in a SPI-like protocol. The timing and transfer protocol is described in
Section 30.9.6,
Transfer formats . The received serial frames are converted to a parallel form (deserialized) and placed on
the Parallel Output signals or in the DSPI_DDR. The various features of the DSI configuration are set in
the DSPI DSI Configuration Register (DSPI_DSICR).
The DSI frames can be from 4 to 32 bits. With Multiple Transfer Operation (MTO) the DSPI supports
serial chaining of DSPI modules within a device to create DSI frames up to 64 bits, consisting of
concatenated bits from multiple DSPIs. The DSPI also supports parallel chaining allowing several DSPIs
and off-chip SPI devices to share the same Serial Communications Clock (SCK) and Peripheral Chip
Select (PCS) signals. See
Section 30.9.3.6, Multiple transfer operation (MTO) , for details on the serial and
parallel chaining support.
30.9.3.1 DSI Master mode
In DSI master mode the DSPI initiates and controls the DSI transfers. The DSI master has four different
conditions that can initiate a transfer:
• Continuous
• Change in data