NXP Semiconductors MPC5644A, Reference Manual, Page: 1257 / 1735

Deserial Serial Peripheral Interface (DSPI)
MPC5644A Microcontroller Reference Manual, Rev. 6
Freescale Semiconductor 1257
30.7 External signal description
30.7.1 Overview
Table 30-2 lists the signals that may connect off-chip depending on the device implementation.
30.7.2 Detailed signal description
30.7.2.1 DSPI_x_PCS[0]/SS — Peripheral Chip Select/Slave Select
In master mode, the DSPI_x_PCS[0] signal is a Peripheral Chip Select output that selects which slave
device the current transmission is intended for.
In slave mode, the active low SS signal is a Slave Select input signal that allows a SPI master to select the
DSPI as the target for transmission.
30.7.2.2 DSPI_x_PCS[1] – PCS[3] — Peripheral Chip Selects 1 – 3
DSPI_x_PCS[1] – PCS[3] are Peripheral Chip Select output signals in master mode. In slave mode these
signals are unused.
30.7.2.3 DSPI_x_PCS[4]/MTRIG — Peripheral Chip Select 4/Master Trigger
In master mode, DSPI_x_PCS[4] is a Peripheral Chip Select output signal.
In slave mode, the active low MTRIG is an output trigger signal that indicates that a change in data to be
serialized has occurred. The MTRIG provides a pulse in DSI configuration when a change in data to be
serialized occurs. The MTRIG pulse is four system clock cycles in duration. If the DSPI is in slave mode
and the MTO is disabled, the DSPI_x_PCS[4]/MTRIG signal is unused.
Table 30-2. Signal properties
Name I/O type
Function
Master mode Slave mode
DSPI_x_PCS[0]/SS Output / Input Peripheral Chip Select 0 Slave Select
DSPI_x_PCS[1] – PCS[3] Output Peripheral Chip Select 1 – 3 Unused
DSPI_x_PCS[4]/MTRIG Output Peripheral Chip Select 4 Master Trigger
DSPI_x_PCS[5]/PCSS Output Peripheral Chip Select 5 /
Peripheral Chip Select Strobe
Unused
DSPI_x_SIN Input Serial Data In Serial Data In
DSPI_x_SOUT Output Serial Data Out Serial Data Out
DSPI_x_SCK Output / Input Serial Clock (output) Serial Clock (input)
HT Input Hardware Trigger Hardware Trigger