NXP Semiconductors MPC5644A, Reference Manual, Page: 123 / 1735

Device Performance Optimization
MPC5644A Microcontroller Reference Manual, Rev. 6
Freescale Semiconductor 123
Note that configuration of the cache has to be performed in conjunction with configuration of the Memory
Management unit. Refer to section
6.3.6, Memory management unit (MMU) .
6.3.6 Memory management unit (MMU)
6.3.6.1 Description
The Memory Management Unit is a 32-bit Power Architecture compliant implementation which provides
functionality that includes address translation and application of access attributes to memory ranges
defined in Translation Lookaside Buffer entries. Although the MMU does not directly impact
performance, it is within the MMU that memory regions are configured to permit the use of system cache
to improve performance and Variable Length Encoding (VLE) to enhance code density. Thus it is essential
that the MMU is correctly configured to ensure optimal application performance is achieved.
6.3.6.1.1 Recommended configuration
The core uses MMU Assist Registers (MASx) which are special purpose registers to facilitate reading,
writing and searching the Translation Lookaside Buffer (TLB) entries. These MAS registers are software
managed by
tlbre , tlbwe , tlbsx , tlbsync , and tlbivax instructions. Refer to the core reference manual for
full details of the MMU and its configurations.
There are several MMU Assist Register registers (MAS0–3) that require configuring. Details of these are
provided in the e200z4 Power Architecture® Core Reference Manual. Specifically, the MAS2 register
contains the fields to control whether a specified memory region described by the valid TLB Entry is cache
inhibited or whether VLE encoding is valid.
ICE Instruction Cache Enable
0: Cache is disabled
1: Cache is enabled
When disabled, cache lookups are not performed for instruction accesses.
Other L1CSR0 cache control operations are still available.
EPN 0
VLE
W I M G E
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
SPR - 626; Read/Write
Figure 6-3. MMU Assist Register 2 (MAS2)
Table 6-3. MAS2 field descriptions
Field Description
EPN Effective page number [0:21]
Table 6-2. L1CSR1 field descriptions (continued)
Field Description