NXP Semiconductors MPC5644A, Reference Manual, Page: 1188 / 1735

Decimation Filter
MPC5644A Microcontroller Reference Manual, Rev. 6
1188 Freescale Semiconductor
Table 26-12. DECFILTER_MXCR Register Field Descriptions
Field Description
0
SDMAE
Integrator DMA Enable. The SDMAE bit enables the DMA request when an integrator output is
requested (see
Section 26.5.15.2, Integrator outputs ”).
1 integrator DMA request enabled
0 integrator DMA request disabled
Note: The DMA channel used is the same one used for filter outputs, and any configuration that
generates DMA requests from both of those sources is not allowed.
1
SSIG
Integrator Signal operation selection. The SSIG bit defines how the filtered data signal is treated
for integration:
1 integrator input takes signaled filter output
0 integrator input takes the absolute value of filter output
2
SSAT
Integrator Saturated operation selection. The SSAT bit defines how the integrator accumulator
behaves in case of an overflow.
1 integrator accumulator saturates on an overflow
0 integrator accumulator holds a modulo 2
17
value (considering the 15-bit fractional part) on an
overflow.
Note: In saturated operation the overflown integration sum holds the value 0xFFFFFFFF for
absolute integration (SSIG = 0), or values 0x7FFFFFFF (positive saturation) and
0x80000000 (negative saturation) for signaled integration (SSIG = 1). Non-saturated
mode is not supported with signaled integration, therefore one must not configure
SSIG = 1 and SSAT = 0.
3
SCSAT
Integrator Counter Saturated operation selection. The SCSAT bit defines how the integrator
sample counter behaves in case of an overflow.
1 integrator sample counter saturates on an overflow, holding a value of 0xFFFFFFFF.
0 integrator sample counter holds a modulo 2
32
value on an overflow.
4–13 Reserved, should be cleared.
14
SRQ
Integrator Output Request. The SRQ bit is used to command the update of the integrator output,
reflected in the registers DECFILTER_FINTVAL and DECFILTER_FINTCNT. It may also cause
a DMA or interrupt request, depending on the DECFILTER_MCR bit SDIE and
DECFILTER_MXCR bit SDMAE. This is a write-only bit, so reads always return 0. For more
details see
Section 26.5.15.2, Integrator outputs ”.
1 requests integrator output update
0 no integrator output update request
15
SZRO
Integrator Zero. The SZRO bit is used to zero the integrator sum. This is a write-only bit, reads
always return 0. For more details see
Section 26.5.15.3, Integrator reset ”.
1 zeroes integrator sum
0 does not zero integrator sum
Note: If bits SRQ and SZRO are both written 1 at the same time, the integrator is reset only after
the registers DECFILTER_FINTVAL and DECFILTER_FINTCNT are updated.
16
SISEL
Integrator Input Selection. The SISEL bit selects the input of the integrator. For more details see
Section 26.5.15.1, Integrator inputs ”.
1 filter outputs before the decimation feed the integrator
0 decimated filter outputs feed the integrator
17 Reserved, should be cleared.