NXP Semiconductors MPC5644A, Reference Manual, Page: 1151 / 1735

Enhanced Queued Analog-to-Digital Converter (EQADC)
MPC5644A Microcontroller Reference Manual, Rev. 6
Freescale Semiconductor 1151
25.6.11 Analog Sub-Block
25.6.11.1 Analog to Digital Converter (ADC)
25.6.11.1.1 ADC architecture
Figure 25-91. RSD ADC Block Diagram
The RSD Cyclic ADC consists of two main portions, the analog RSD Stage, and the digital control and
calculation block, as shown in
Figure 25-91 . To begin an analog to digital conversion, a differential input
is passed into the analog RSD stage. The signal is passed through the RSD stage, and then from the RSD
stage output, back to its input to be passed again. To complete a 12-bit conversion, the signal must pass
through the RSD stage 12 times. For 10-bit and 8-bit resolution, the signal must pass 10 or 8 times through
the RSD. Each time an input signal is read into the RSD stage, a digital sample is taken by the digital
control/calculation block. The digital control/calculation block uses this sample to tell the analog block
how to condition the signal. The digital block also saves each successive sample and adds them according
to the RSD algorithm at the end of the entire conversion cycle.
RSD SINGLE-STAGE
DIGITAL CONTROL
AND CALCULATION
pipeline_control
sample
12 bit
OUTPUT
DIFF
INPUT
CLOCK
PIPELINE