NXP Semiconductors MPC5644A, Reference Manual, Page: 1073 / 1735

Enhanced Queued Analog-to-Digital Converter (EQADC)
MPC5644A Microcontroller Reference Manual, Rev. 6
Freescale Semiconductor 1073
Figure 25-48. Command Flow during EQADC operation
ADC commands sent to the on-chip CBuffers are executed in a first-in-first-out basis with exception when
the immediate conversion command function is enabled. Three types of results can be expected: data read
from an ADC register, a conversion result, or a time stamp. The order at which ADC commands sent to
the external device are executed, and the type of results that can be expected depends on the architecture
of that device with the exception of unsolicited data like null messages for example.
NOTE
While the EQADC pops commands out from a CFIFO, it also is checking
the number of entries in the CFIFO and generating requests to fill it. The
process of pushing and popping commands to and from a CFIFO can occur
simultaneously. However, this is not true for CFIFO0 when configured to
operate in streaming mode for popping.
The FIFO Control Unit expects all incoming results to be shaped in a predefined Result Message format.
Figure 25-49 shows how result data flows inside the EQADC system. Results generated on the on-chip
ADCs are adjusted considering the selected resolution of the ADC and are formatted into result messages
inside the
Result Format and Calibration Sub-Block . This result message can be routed directly to one of
the RFIFOs or to an on-chip companion module via the parallel side interface. After the data is processed
by the companion module, it can be routed back to one of the RFIFOs via the side interface with the correct
format. Results returning from the external device are already formatted into result messages and therefore
bypass the
Result Format and Calibration Sub-Block . A result message is composed of an RFIFO header
Priority
CFIFOx
NOTE: x=0, 1, 2, 3, 4, 5
32 bits
CQueuey CBuffer
Inside EQADC
FIFO Control
To
ADCs
Command Message
CFIFO Header
ADC Command
Host CPU
or
DMAC
32 bits
DMA or interrupt requests
ADC
y=0, 1, 2, 3, ...
System Memory
ADC
External Device
Logic
&
Buffers
EQADC SSI
EQADC SSI
DMA Transaction
Done Signals
Unit
Abort
Cont