NXP Semiconductors MPC5644A, Reference Manual, Page: 1074 / 1735

Enhanced Queued Analog-to-Digital Converter (EQADC)
MPC5644A Microcontroller Reference Manual, Rev. 6
1074 Freescale Semiconductor
and an ADC Result. The FIFO Control Unit decodes the information contained in the RFIFO header to
determine the RFIFO to which the ADC result should be sent. Once in an RFIFO, the ADC result is moved
to the corresponding RQueue by the host CPU or by the DMAC as they respond to interrupt and DMA
requests generated by the EQADC. The EQADC generates these requests whenever an RFIFO has at least
one entry.
NOTE
While conversion results are returned, the EQADC is checking the number
of entries in the RFIFO and generating requests to empty it. The process of
pushing and popping ADC results to and from an RFIFO can occur
simultaneously.
Figure 25-49. Result Flow during EQADC operation
25.6.2.2 Assumptions/Requirements Regarding the External Device
The external device exchanges command and result data with the EQADC through the EQADC SSI
interface. This section explains the minimum requirements an external device has to meet to properly
NOTE: x=0, 1, 2, 3, 4, 5
Inside EQADC
Host CPU
or
DMAC
ADC
y=0, 1, 2, 3, ...
System Memory
EQADC SSI
External Device
Decoder
RQueue y
RFIFOx
16 bits
16 bits
ADC
Result Message
RFIFO Header
ADC Result
Logic
&
Buffers
EQADC SSI
DMA or interrupt requests
DMA Transaction
Done Signals
FIFO Control
Unit
Result
Format and
Calibration
Sub-Block
On-Chip
Companion
EQADC PSI
Module
Resolution
Ad
just