NXP Semiconductors MPC5605BK, Reference Manual

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Chapter 26 Deserial Serial Peripheral Interface (DSPI)
MPC5606BK Microcontroller Reference Manual, Rev. 2
594 Freescale Semiconductor
Figure 26-2 shows a DSPI with external queues in internal SRAM.
Figure 26-2. DSPI with queues and eDMA
26.2 Features
The DSPI supports these SPI features:
• Full-duplex, three-wire synchronous transfers
• Master and slave mode
• Buffered transmit and receive operation using the TX and RX FIFOs, with depths of four entries
• Visibility into TX and RX FIFOs for ease of debugging
• FIFO bypass mode for low-latency updates to SPI queues
• Programmable transfer attributes on a per-frame basis
— Six clock and transfer attribute registers
— Serial clock with programmable polarity and phase
— Programmable delays
– CS to SCK delay
– SCK to CS delay
– Delay between frames
— Programmable serial frame size of 4 to 16 bits, expandable with software control
— Continuously held chip select capability
• As many as six peripheral chip selects, expandable to 64 with external demultiplexer
• Deglitching support for as many as 32 peripheral chip selects with external demultiplexer
• Two DMA conditions for SPI queues residing in RAM or flash
— TX FIFO is not full (TFFF)
— RX FIFO is not empty (RFDF)
• Six interrupt conditions:
Internal SRAM
TX queue
RX queue
Address/control
TX FIFO
DSPI
RX FIFO
RX data
TX data
TX data RX data
Shift register
eDMA controller
Address/control
or host CPU