NXP Semiconductors MPC5605BK, Reference Manual

Page: 530 / 964

Chapter 24 LIN Controller (LINFlexD)
MPC5606BK Microcontroller Reference Manual, Rev. 2
530 Freescale Semiconductor
24.11.5 UART node, TX mode
In UART TX mode, the DMA interface requires a DMA TX channel. A single TCD can control the
transmission of an entire Tx buffer. The memory map associated with the TCD chain (RAM area and
LINFlexD registers) is shown in
Figure 24-51 .
Figure 24-51. TCD chain memory map (UART node, TX mode)
The UART TX buffer must be configured in FIFO mode in order to:
• Allow the transfer of large data buffer by a single TCD
• Adsorb the latency, following a DMA request (due to the DMA arbitration), to move data from the
RAM to the FIFO
• Use low priority DMA channels
• Support the UART baud rate (2 Mb/s) without underrun events
The Tx FIFO size is:
SOFF[15:0] 4 Word increment
SSIZE[2:0] 2 Word transfer
SLAST[31:0] –N
DADDR[31:0] RAM address
DOFF[15:0] 4 Word increment
DSIZE[2:0] 2 Word transfer
DLAST_SGA[31:0] –N No scatter/gather processing
INT_MAJ 0/1 Interrupt disabled/enabled
D_REQ 1 Only on the last TCD of the chain.
START 0 No software request
Table 24-46. TCD settings (slave node, RX mode) (continued)
TCD Field Value Description
BDRL
(M half-words)
BDRL
(2 half-words FIFO mode)
BDRL
(M half-words)
BDRL
(2 half-words FIFO mode)
BDRL
(M bytes)
BDRL
(M bytes)
DMA transfer (8/16-bit data format)
RAM area LINFlex2 registers
1 DMA TX channel (TCD single and/or linked chain)
TCD (n+1)
TCD (n)
Buffer (n+1)
BDRL
(4 bytes FIFO mode)
BDRL
(4 bytes FIFO mode)
Buffer (n)