NXP Semiconductors MPC5605BK, Reference Manual

Page: 265 / 964

Chapter 16 Enhanced Direct Memory Access (eDMA)
MPC5606BK Microcontroller Reference Manual, Rev. 2
Freescale Semiconductor 265
16.3.2.8 DMA Clear Enable Error Interrupt (EDMA_CEEIR)
The EDMA_CEEIR provides a memory-mapped mechanism to clear a given bit in the EDMA_EEIRL to
disable the error interrupt for a given channel. The data value on a register write causes the corresponding
bit in the EDMA_EEIRL to be cleared. Setting bit 1 (CEEI[0]) provides a global clear function, forcing
the entire contents of the EDMA_EEIRL to be zeroed, disabling error interrupts for all channels. Reads of
this register returns all zeroes. See
Figure 16-9 and Table 16-9 for the EDMA_CEEIR definition.
16.3.2.9 DMA Clear Interrupt Request (EDMA_CIRQR)
The EDMA_CIRQR provides a memory-mapped mechanism to clear a given bit in the EDMA_IRQRL to
disable the interrupt request for a given channel. The given value on a register write causes the
corresponding bit in the EDMA_IRQRL to be cleared. Setting bit 1 (CINT[0]) provides a global clear
function, forcing the entire contents of the EDMA_IRQRL to be zeroed, disabling all eDMA interrupt
requests. Reads of this register return all zeroes. See
Figure 16-10 and Table 16-10 for the EDMA_CIRQR
definition.
Offset: 0x001B Access: Write
0 1 2 3 4 5 6 7
R 0 0 0 0 0 0 0 0
W CEEI[0:6]
RESET: 0 0 0 0 0 0 0 0
Figure 16-9. DMA Clear Enable Error Interrupt (EDMA_CEEIR) Register
Table 16-9. EDMA_CEEIR field descriptions
Field Description
CEEI Clear Enable Error Interrupt
0–63 Clear corresponding bit in EDMA_EEIRL
64–127 Clear all bits in EDMA_EEIRL
Offset: 0x001C Access: Write
0 1 2 3 4 5 6 7
R 0 0 0 0 0 0 0 0
W CINT
RESET: 0 0 0 0 0 0 0 0
Figure 16-10. DMA Clear Interrupt Request (EDMA_CIRQR) Fields
Table 16-10. EDMA_CIRQR field descriptions
Field Description
CINT[0:6] Clear Interrupt Request
0–63 Clear the corresponding bit in EDMA_IRQRL
64–127 Clear all bits in EDMA_IRQRL