NXP Semiconductors MPC5605BK, Reference Manual

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Chapter 8 Mode Entry Module (MC_ME)
MPC5606BK Microcontroller Reference Manual, Rev. 2
Freescale Semiconductor 171
8.4.3.9 Pad outputs-on
On completion of the Main voltage regulator switch-on , if the PDO bit of the ME_ <target mode> _MC
register is cleared, then
• All pad outputs are enabled to return to their previous state
• The I/O pads power sequence driver is switched on
8.4.3.10 Processor and memory clock enable
If the mode transition is from any of the low-power modes HALT or STOP to RUN0…3, the clocks to the
processor and system memories are enabled. The process of enabling these clocks is executed only after
the
Flash modules switch-on process is completed.
8.4.3.11 Processor low-power mode exit
If the mode transition is from any of the low-power modes HALTSTOP to RUN0…3, the MC_ME
requests the processor to exit from its halted or stopped state. This step is executed only after the
Processor
and memory clock enable process is completed.
8.4.3.12 System clock switching
Based on the SYSCLK bit field of the ME_ <current mode> _MC and ME_ <target mode> _MC registers,
if the target and current system clock configurations differ, the following method is implemented for clock
switching.
• The target clock configuration for the 16 MHz int. RC osc. is effective only when the S_FIRC bit
of the ME_GS register is set by hardware (i.e. the fast internal RC oscillator (16 MHz) has
stabilized).
• If the clock is to be disabled, the SYSCLK bit field should be programmed with 1111. This is
possible only in the TEST mode.
The current system clock configuration can be observed by reading the S_SYSCLK bit field of the ME_GS
register, which is updated after every system clock switching. Until the target clock is available, the system
uses the previous clock configuration.
System clock switching starts only after
• The Clock sources switch-on process has completed if the target system clock source needs to be
switched on
An overview of system clock source selection possibilities for each mode is shown in Table 8-13 . A

indicates that a given clock source is selectable for a given mode.