NXP Semiconductors MPC5566, Reference Manual

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Deserial Serial Peripheral Interface (DSPI)
MPC5566 Microcontroller Reference Manual, Rev. 2
20-70 Freescale Semiconductor
The following delay variables generate the same delay, or as close as possible, from the DSPI 100 MHz
system clock that an MPC5xx family part generates from a 40 MHz system clock. For other system clock
frequencies, you can recompute the values using the information presented in
Section 20.5.3, “Delay
Settings .”
For BITSE = 0 --> 8 bits per transfer
For DT = 0 --> 0.425
μ
s delay: for this value, the closest value in the DSPI is 0.480
μ
s
For DSCK = 0 --> 0.5 of the SCK period: for this value, the value for the DSPI is 20 ns
20.5.5 Calculation of FIFO Pointer Addresses
The user has complete visibility of the TX and RX FIFO contents through the FIFO registers, and valid
entries can be identified through a memory mapped pointer and a memory mapped counter for each FIFO.
The pointer to the first-in entry in each FIFO is memory mapped. For the TX FIFO the first-in pointer is
the transmit next pointer (TXNXTPTR). For the RX FIFO the first-in pointer is the pop next pointer
(POPNXTPTR).
See Section 20.4.3.4, “Using the TX FIFO Buffering Mechanism ,” and Section 20.4.3.5, “Using the RX
FIFO Buffering Mechanism ,” for details on the FIFO operation. The TX FIFO is chosen for the
illustration, but the concepts carry over to the RX FIFO.
Table 20-33. MPC5xx QSPI Compatibility with the DSPI
MPC5xx Family Control Bits
DSPI Corresponding Control Bits
Corresponding DSPI x _CTAR Register Configuration
BITSE CTAS[0] DT CTAS[1] DSCK CTAS[2] DSPI x _CTAR x FMSZ PDT DT PCSSCK CSSCK
0 0 0 0 0111 10 0011 00 0000
0 0 1 1 0111 10 0011 User User
0 1 0 2 0111 User
1
1
Selected by user
User 00 0000
0 1 1 3 0111 User User User User
1 0 0 4 User 10 0011 00 0000
1 0 1 5 User 10 0011 User User
1 1 0 6 User User User 00 0000
1 1 1 7 User User User User User