NXP Semiconductors MPC5566, Reference Manual

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Deserial Serial Peripheral Interface (DSPI)
MPC5566 Microcontroller Reference Manual, Rev. 2
20-38 Freescale Semiconductor
20.4.3.3 FIFO Disable Operation
The FIFO disable mechanisms allow SPI transfers without using the TX FIFO or RX FIFO. The DSPI
operates as a double-buffered simplified SPI when the FIFOs are disabled. The TX and RX FIFOs are
disabled separately. The TX FIFO is disabled by writing a 1 to the DIS_TXF bit in the DSPI
x _MCR. The
RX FIFO is disabled by writing a 1 to the DIS_RXF bit in the DSPI x _MCR.
The FIFO disable mechanisms are transparent to the user and to host software; transmit data and
commands are written to the DSPI
x _PUSHR and received data is read from the DSPI x _POPR. When the
TX FIFO is disabled, the TFFF, TFUF, and TXCTR fields in DSPI x _SR behave as if there is a one-entry
FIFO but the contents of the DSPI x _TXFRs and TXNXTPTR are undefined. When the RX FIFO is
disabled, the RFDF, RFOF, and RXCTR fields in the DSPI x _SR behave as if there is a one-entry FIFO but
the contents of the DSPI x _RXFRs and POPNXTPTR are undefined.
Disable the TX and RX FIFOs only if the FIFO must be disabled as a requirement of the application's
operating mode. A FIFO must be disabled before it is accessed. Failure to disable a FIFO prior to a first
FIFO access is not supported, and can result in incorrect results.
20.4.3.4 Using the TX FIFO Buffering Mechanism
The TX FIFO functions as a buffer of SPI data and SPI commands for transmission. The TX FIFO holds
four entries, each consisting of a command field and a data field. SPI commands and data are added to the
TX FIFO by writing to the DSPI push TX FIFO register (DSPI
x _PUSHR). For more information on
DSPI x _PUSHR. TX FIFO entries can only be removed from the TX FIFO by being shifted out or by
flushing the TX FIFO.
See Section 20.3.2.6, “DSPI PUSH TX FIFO Register (DSPIx_PUSHR) .”
The TX FIFO counter field (TXCTR) in the DSPI status register (DSPI x _SR) indicates the number of valid
entries in the TX FIFO. The TXCTR is updated every time the DSPI _PUSHR is written or SPI data is
transferred into the shift register from the TX FIFO.
See Section 20.3.2.4, “DSPI Status Register (DSPIx_SR) ” for more information on DSPI x _SR.
The TXNXTPTR field indicates which TX FIFO entry is transmitted during the next transfer. The
TXNXTPTR contains the positive offset from DSPI
x _TXFR0 in number of 32-bit registers. For example,
TXNXTPTR equal to two means that the DSPI x _TXFR2 contains the SPI data and command for the next
transfer. The TXNXTPTR field is incremented every time SPI data is transferred from the TX FIFO to the
shift register.
20.4.3.4.1 Filling the TX FIFO
Host software or the eDMA controller can add (push) entries to the TX FIFO by writing to the
DSPI
x _PUSHR. When the TX FIFO is not full, the TX FIFO fill flag (TFFF) in the DSPI x _SR is set. The
TFFF bit is cleared when the TX FIFO is full and the eDMA controller indicates that a write to
DSPI
x _PUSHR is complete or alternatively by host software writing a 1 to the TFFF in the DSPI x _SR.
The TFFF can generate a DMA request or an interrupt request.
See Section 20.4.9.2, “Transmit FIFO Fill Interrupt or DMA Request (TFFF) ,” for details.