NXP Semiconductors MPC5566, Reference Manual

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Deserial Serial Peripheral Interface (DSPI)
MPC5566 Microcontroller Reference Manual, Rev. 2
Freescale Semiconductor 20-41
20.4.4.2 DSI Slave Mode
In DSI slave mode the DSPI responds to transfers initiated by an SPI or DSI bus master. In this mode the
DSPI does not initiate DSI transfers. Certain transfer attributes such as clock polarity and phase must be
set for successful communication with a DSI master. The DSI slave mode transfer attributes are set in the
DSPI
x _CTAR1.
If the CID bit in the DSPI x _DSICR is set and the data in the DSPI x _COMPR differs from the selected
source of the serialized data, the slave DSPI asserts the MTRIG signal. If the slave’s internal hardware
trigger signal is asserted and the TRRE is set, the slave DSPI asserts MTRIG. These features are included
to support chaining of several DSPI. Details about the MTRIG signal are found in
Section 20.4.4.7,
“Multiple Transfer Operation (MTO) .”
20.4.4.3 DSI Serialization
In the DSI configuration, 4 to 16 bits can be serialized using two different sources. The TXSS bit in the
DSPI
x _DSICR selects between the DSPI x _SDR and DSPI x _ASDR as the source of serialized data. See
Section 20.3.2.11, “DSPI DSI Serialization Data Register (DSPIx_SDR) ,” and Section 20.3.2.12, “DSPI
DSI Alternate Serialization Data Register (DSPIx_ASDR) ,” for more details. The DSPI x _SDR holds the
latest parallel input signal values which is sampled at every rising edge of the system clock. The
DSPI
x _ASDR is written by host software and used as an alternate source of serialized data.
A copy of the last DSI frame shifted out of the shift register is stored in the DSPI x _COMPR. This register
provides added visibility for debugging and it serves as a reference for transfer initiation control.
Section 20.3.2.13, “DSPI DSI Transmit Comparison Register (DSPIx_COMPR) ,” contains details on the
DSPI x _COMPR.
Figure 20-19 shows the DSI serialization logic.
Figure 20-19. DSI Serialization Diagram
1
0
DSPI alternate
serialization data register
SOUT x
Parallel
DSI configuration
register
DSI transmit
comparison register
Clock
logic
0 1 • • • • • 15
Shift register
DSI serialization
data register
Control
logic
SCK x
inputs
PCS x
ht
16
16
16
16
TXSS
Slave bus interface
16