NXP Semiconductors MPC5566, Reference Manual

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Enhanced Time Processing Unit (eTPU)
MPC5566 Microcontroller Reference Manual, Rev. 2
18-42 Freescale Semiconductor
where:
18.4.6.2 eTPU Channel n Configuration Register (ETPU_C n CR)
The ETPU_C n CR is a collection of the configuration bits related to an individual channel. Some of these
bits are mirrored from the global channel registers.
Address: Channel_Registe 0x0000 Access: R/W
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
R
CIE DTRE CPR
0 0
ETPD
1
ETCS
0 0 0
CFS
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R
ODIS OPOL
0 0 0
CPBA
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
1
ETPD is not available on the MPC5566.
Figure 18-22. ETPU Channel n Configuration Register (ETPU_C n CR
)
Table 18-25. ETPU_C n CR Field Descriptions
Field Description
0
CIE
Channel interrupt enable. This bit is mirrored from the ETPU_CIER
0 Disable interrupt for this channel.For more information, refer to the
eTPU Reference Manual .
1 Enable interrupt for this channel.
1
DTRE
Channel data transfer request enable. This bit is mirrored from the ETPU_CDTRER.
0 Disable data transfer request for this channel.Refer to the
eTPU Reference Manual for more information.
1 Enable data transfer request for this channel.
Channel_Register_Structure_Base_Address ETPU_Engine_Channel_Base channel_number 0x0000_0010
×
( )
+ =
ETPU_Engine_Channel_Base ETPU_Base 0x0000_0400 ETPU A =
( )
or 0x0000_0800 ETPU B =
( ) ( )
+ =