NXP Semiconductors MPC5566, Reference Manual

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Enhanced Time Processing Unit (eTPU)
MPC5566 Microcontroller Reference Manual, Rev. 2
Freescale Semiconductor 18-41
18.4.6.1 Channel Registers Layout
One contiguous area is used to map all channel registers of each eTPU engine as shown in Table 18-24 .
There are 64 structures defined, one for each available channel in the eTPU System (32 for each engine).
The base address for the structure presented can be calculated by using the following equation:
Table 18-23. Channel Registers Structure
Channel
Offset
Register Name
0x0000 eTPU channel configuration register (ETPU_C n CR)
0x0004 eTPU channel status/control register
1
(ETPU_C n SCR)
1
In the MPC5566, eTPU A channels [0:2,12:15,28:29] and eTPU B channels
[0:3,12:15,28:31] are connected to the DMA. The data transfer request lines that
are not connected to the DMA controller are left disconnected and do not generate
interrupt requests, even if their request status bits assert in registers
ETPU_CDTRSR and ETPU_C
n SCR.
0x0008 eTPU channel host service request register (ETPU_C n HSRR)
0x000C Reserved
Table 18-24. eTPU Channel Register Map
Address Registers Structure
Base + 0x0000_0400 eTPU A channel 0 register structure
Base + 0x0000_0410 eTPU A channel 1 register structure
Base + 0x0000_0420 eTPU A channel 2 register structure
Base + (0x0000_0430–0x0000_05D0)
.
.
.
Base + 0x0000_05E0 eTPU A channel 30 register structure
Base + 0x0000_05F0 eTPU A channel 31 register structure
Base + (0x0000_0600–0x0000_07FF) Reserved
Base + 0x0000_0800 eTPU B channel 0 register structure
Base + 0x0000_0810 eTPU B channel 1 register structure
Base + 0x0000_0820 eTPU B channel 2 register structure
Base + (0x0000_0830–0x0000_09D0)
.
.
.
Base + 0x0000_09E0 eTPU B channel 30 register structure
Base + 0x0000_09F0 eTPU B channel 31 register structure
Base + (0x0000_00A0–0x0000_0BFF) Reserved