
Enhanced Modular Input/Output Subsystem (eMIOS)
MPC5566 Microcontroller Reference Manual, Rev. 2
Freescale Semiconductor
17-35
describes the A1 and B1 register updates when EMIOS_CADR
n
and EMIOS_CBDR
n
read
operations are performed. When an EMIOS_CADR
n
read occurs the content of A1 is transferred to B1
thus providing coherent data in the A2 and B1 registers. Transfers from B2 to B1 are then blocked until
EMIOS_CBDR
n
is read. After EMIOS_CBDR
n
is read, register A1 content is transferred to register B1
and the transfers from B2 to B1 are re-enabled to occur at the transfer edges, which is the leading edge in
the
Figure 17-22. A1 and B1 Updates at EMIOS_CADR and EMIOS_CBDR Reads
17.4.4.4.6
Double-action Output Compare Mode (DAOC)
The following table lists the double-action output compare mode settings:
In the DAOC mode the leading and trailing edges of the variable pulse-width output are generated by
matches occurring on comparators A and B, respectively.
When the DAOC mode is first selected (coming from GPIO mode) both comparators are disabled.
Comparators A and B are enabled by updating registers A1 and B1 respectively and remain enabled until
a match occurs on that comparator, when it is disabled again. To update registers A1 and B1, a write to A2
and B2 must occur and the EMIOS_CCR
n
[ODIS] bit must be cleared.
The output flip-flop is set to the value of EMIOS_CCR
n
[EDPOL] when a match occurs on comparator A
and to the complement of EDPOL when a match occurs on comparator B.
Table 17-19. DAOC Operating Modes
MODE[0:6]
Unified Channel DAOC
Operating
Mode
0b0000110
Double-action output compare (with FLAG set on the second match)
0b0000111
Double-action output compare (with FLAG set on both matches)
0x000500
0x001000
0x001100
0x001250
0x001525
0x0016A0
Selected
counter bus
FLAG
set event
A
A
A
Captured A2
value
2
0xxxxxxx
Notes:
1
After input filter.
2
Reading EMIOS_CADR
n
returns the value of A2.
Input signal
1
EDPOL = 1
B1 value
3
0x001525
0xxxxxxx
0xxxxxxx
0x001000
0x001250
Captured B2
value
3
Reading EMIOS_CBDR
n
returns the value of B1.
0xxxxxxx
0x001000
0x001250
A1 value
Read MTSA[n]
Read MTSB[
n
]
0x001250
0x001000
0x001000
0x0016A0
0x001100
0x001250
Summary of Contents for MPC5566
Page 81: ...Introduction MPC5566 Microcontroller Reference Manual Rev 2 1 24 Freescale Semiconductor...
Page 135: ...Signal Description MPC5566 Microcontroller Reference Manual Rev 2 2 54 Freescale Semiconductor...
Page 189: ...Reset MPC5566 Microcontroller Reference Manual Rev 2 4 20 Freescale Semiconductor...
Page 603: ...Flash Memory MPC5566 Microcontroller Reference Manual Rev 2 13 38 Freescale Semiconductor...
Page 609: ...SRAM MPC5566 Microcontroller Reference Manual Rev 2 14 6 Freescale Semiconductor...
Page 1073: ...MPC5566 Microcontroller Reference Manual Rev 2 22 36 Freescale Semiconductor...
Page 1185: ...Nexus MPC5566 Microcontroller Reference Manual Rev 2 25 92 Freescale Semiconductor...