NXP Semiconductors MPC5566, Reference Manual

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External Bus Interface (EBI)
MPC5566 Microcontroller Reference Manual, Rev. 2
12-72 Freescale Semiconductor
Figure 12-49 shows a 32-bit write from an external master in 16-bit data bus mode.
Figure 12-49. External Master 32-bit Write to MCU with DBM = 1
12.4.2.12 Calibration Bus Operation
The EBI has a second external bus, intended for calibration use. This bus consists of a second set of the
same signals present on the primary external bus, except that arbitration, (and optionally other signals also)
are excluded. Both busses are supported by the EBI by using the calibration chip selects to steer accesses
to the calibration bus instead of to the primary external bus.
Because the calibration bus has no arbitration signals, the arbitration on the primary bus controls accesses
on the calibration bus as well, and no external master accesses can be performed on the calibration bus.
Accesses cannot be performed in parallel on both external busses. However, back-to-back accesses can
switch from one bus to the other, as determined by the type of chip select each address matches.
The timing diagrams and protocol for the calibration bus are identical to those for the primary bus, except
that some signals are not available on the calibration bus. There is an inherent dead cycle between a
calibration chip select access and a non-calibration access (chip select or non-chip select), just like the one
between accesses to two different non-calibration chip selects (described in
Section 12.4.2.4.3,
“Back-to-Back Accesses ”).
Figure 12-50 shows an example of a non-calibration chip select read access followed by a calibration chip
select read access. This figure is identical to Figure 12-18 , except the CS[ y ] is replaced by CAL_CS[ y ].
Timing for other cases on the calibration bus can similarly be derived from other figures in this document
(by replacing CS with CAL_CS).
DATA is valid
Receive bus grant and bus busy
negated for second cycle
Assert BB drive address
and assert TS
Using the internal arbiter
CLKOUT
BR (Input)
RD_WR
TSIZ[0:1]
BDIP
BG
BB
ADDR[8:31]
DATA[0:15]
TS (Input)
Minimum
three wait states
TA (Output)
‘00’
DATA is valid